Data path tradeoffs using MABAL

2002

The paper presents a parametric module design framework that is suitable for datapatNDSP soft-IP design. This framework is based on the integration of various frequently used parametric module generators. Under this design framework, system or circuit designers specify the structural information of the modules in C++, and then compile and co-simulate with any C/C++ programs/algorithms. Furthermore, they can manually adjust the simulation model whenever necessary. Once the system design is completed, an efficient gate-level Verilog code can soon be generated automatically. By examining the system functionality using high-level language and automatically translating the design entries into gate-level description, we can easily keep our design effort at system level while maintaining a tight consistency between different levels of abstraction. Therefore the proposed framework yields a fast, robust, and cost-effective solution to high-complexity datapath/DSP module design.

Proc. 9th VLSI Design …, 2005

Today's VLSI technology allows us to construct large, complex systems with million transistors on a single chip. Most of the existing high level synthesis systems give more priority to optimization of area, power, resource and time steps compared to interconnection cost, whereas the later becomes predominant with the technology scaling and increase in complexity. Further, field programmable gate arrays (FPGA) are now becoming attractive platform for prototyping. Programmable devices tend to have limited wiring resources between the data path elements. This work is concerned with the development of a CAD tool for HLS named, "Structured Architecture Synthesis Tool (SAST)", which incorporates structured architecture generation with special emphasis on optimization of interconnect area. The too takes a behavioral description written in 3-address form and generates synthesizable RTL codes with scripts for compliance with standard design tools like Synopsys, Magma etc.

2009 Asia and South Pacific Design Automation Conference, 2009

While technology scaling has presented many new and exciting opportunities, new design challenges have arisen due to increased density, and delay and power variations. Highlevel synthesis has been touted as a solution to these problems, as it can significantly reduce the number of man hours required for a design by raising the level of abstraction. In this paper, we propose a new variation-aware high-level synthesis binding/module selection algorithm, named FastYield, which takes into consideration multiplexers, functional units, registers, and interconnects. Additionally, FastYield connects with the lower levels of the design hierarchy through its inclusion of a timing driven floorplanner guided by a statistical static timing analysis (SSTA) engine which is used to modify/enhance the synthesis solution. FastYield is able to incorporate spatial correlations of process variations in its optimization, which are shown to affect performance yield. On average, FastYield achieves a clock period that is 14.5% smaller, and a performance yield gain of 78.9%, when compared to a variation-unaware algorithm. By making use of accurate timing information, FastYield's rebinding improves performance yield by an average of 9.8% over the initial binding, for the same clock period. To the best of our knowledge, this is the first high-level synthesis binding/module selection algorithm that is layout-driven and variation aware.

Proc. of …, 2000

With the advent of deep sub-microntechnologies,interconnectloads and delays are becoming dominant. Consequently, the currently used design ow of iterativelyperforming logic synthesis with statistical wire-load models, doing placement & routing, extracting parasitics, and using them back in the synthesis tool runs into serious timing convergence problems. Layout-driven synthesis has become the need of the day. In this paper, we present a layout-driven optimization methodology that incorporates logic-level transformations for improving the delay and area of a mapped, block-placed, and globally routed design under certain constraints such as area availability, congestion, hold-time, and pin drive, etc. We argue that this is the right stage for optimization. Only those transformations that are local, incremental, and layout-friendly are incorporated. Examples of such transformations are net bu ering, gate resizing, generalized DeMorgan transform, and pin permutation. We propose a simple ow to simultaneously improve the delay and area of the design under these constraints. We applied this ow on large, already optimized, industrial designs and obtained signi cant delay and area improvements.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1995

System-level design involves making major design decisions without having accurate information on the eventual system characteristics. This paper presents a novel constraintdriven methodology to support system-level design. The software assists a designer or a tool in partitioning behavioral specifications onto multiple VLSI chips and in system design while satisfying hard constraints such as individual chip areas, chip pin counts, system throughput (inverse of system initiation interval) and system latency (delay). The software uses search and estimation techniques to perform comprehensive design-space exploration and evaluates partitions supplied by the user or by other synthesis software. The technique determines what design characteristics each partition must possess in order to satisfy area, pin, throughput and latency constraints. The paper also includes results of extensive experiments with the methodology.