Abstract—The design of a cortical neuron with carbon,nan- otube,circuit elements,that performs,no... more Abstract—The design of a cortical neuron with carbon,nan- otube,circuit elements,that performs,nonlinear,dendritic com- putations is presented. The circuit design incorporates CNFETs, and,was,simulated,using carbon,nanotube,spice models.
In a redesign situation, the compatibility of the replacement chips is critical. This can only be... more In a redesign situation, the compatibility of the replacement chips is critical. This can only be obtained by verifying both their functionality and timing. In this report, we will postulate that the general RTL verification problem is too difficult to be solved. Hence, it is necessary for a RTL verification system to trade off generality for usability. In fact, there is a real need for an automatic tool that can check the functional and timing compatibility of automatically synthesized chips quickly and effectively. We found that synthesized designs have several common properties that can be utilized to facilitate this task. By making use of the USC design data structure (DDS) graph models, we developed a hybrid symbolic approach that will not only verify functional compatibility but also take into account the timing and the interaction between the controller and the datapath. Experiments have been performed on two designs, an AR filter and a robot arm controller synthesized by the ADAM system. The results are very encouraging. In fact, these experiments helped to identify problems with the early version of the control signal generator (CSG) software.
This paper describes the REAL REgister ALlocation program. REAL uses a track assignment algorithm... more This paper describes the REAL REgister ALlocation program. REAL uses a track assignment algorithm taken from channel routing called the Left Edge algorithm. REAL is optimal for non-pipelined designs with no conditional branches. It is thought that REAL is also optimal for designs with conditional branches, pipelined or not. Experimental results are included in the report, which illustrate the optimal solutions found by REAL. REAL is part of the ADAM Advanced Design AutoMation system, and will be used to process designs output from MAHA and Sehwa.
This paper describes a processor architecture designed specifically to perform input/output and i... more This paper describes a processor architecture designed specifically to perform input/output and interfacing functions for any central-processor-peripheral configuration. This architecture is justified on the basis of functional I/O requirements which are discussed in detail. This processor is microprogrammable with a writeable control store, allowing dynamic configuration of the processor for different input/ output and interfacing applications. Underlying the microcontrol is a ROM-resident nanoprogram which performs the complex timing, handshaking, and bookkeeping control tasks. The processor architecture is modular and bus oriented.
In this paper, we describe an approach to data-path synthesis from a partitioned behavioral-level... more In this paper, we describe an approach to data-path synthesis from a partitioned behavioral-level description into a multiple-chip pipelined RTL design. The problem is divided into interchip connection determination and scheduling. A heuristic search technique is described for interchip connection determination. Synthesis results are presented.
Proceedings of the 22nd ACM/IEEE conference on Design automation - DAC '85, 1985
Clocking scheme synthesis includes the partitioning of functions into time steps, the number of c... more Clocking scheme synthesis includes the partitioning of functions into time steps, the number of clock phases, the length of each phase, (i.e. how to pipeline) and the assignment of functions to clock phases; each of these choices affects performance. Some important problems of clocking scheme synthesis are examined. Two efficient and powerful algorithms which synthesize near optimal clocking schemes have been programmed. These algorithms are applied to synthesis and/or performance evaluation of a design in progress. Optimizing the speed of a previously designed system is also considered.
This paper presents an approach to predicting the feasibility of artificial brains in the future.... more This paper presents an approach to predicting the feasibility of artificial brains in the future. We focus on biomimetic neural models and electronic circuits that implement those models. Complexities in modeling biological neural tissue are discussed. Estimates are given for the size of artificial neural systems based on CMOS technology in 2021, without considering interconnections. We propose some solutions to the problem of interconnecting neurons. However, the best solution to this issue is an ongoing research topic.
In this paper we present a software package which manages the digital design process using a plan... more In this paper we present a software package which manages the digital design process using a planning paradigm. Under this paradigm design is seen as a process in which abstract models of operators are applied to abstract models of design states in a simulated or planning space, until a sequence of operators has been constructed to completion. The hypothetical design represented by the terminal stat.e is then estimated. Either the planning is then repeated, or the sequence, or plan, is then executed, or carried out, in an execution space. This execution is monitored for violation of expectations; if violations occur, control is returned to the planner. The knowledge base of the planner is populated with register transfer level (RTL) concepts, and it can be populated with other knowledge sets. The planner forms part of t.he USC .4DAM (Advanced Design AutoMation) system. 2. Introduction 2.1. The ADAM System The USC ADAM system' is designed to unify a number of design automation programs into a single framework. The main areas of effort are custom layout, an expert system for the design of testable circuits, a knowledgebased synthesis system, and a database which provides a common representational scheme for designs, programs, and constraints. All design data, procedures, and rule sets are treat,ed as objects, communicating with one another by means of messages.
1.2 The Natural Language Interface This paper describes a natural language interface, PHRAN-SPAN,... more 1.2 The Natural Language Interface This paper describes a natural language interface, PHRAN-SPAN, for specifying the abstract behavior of digital systems in restricted English tezt. A neutral formal representation for the behavior is described using the USC Design Data Structure. A small set of concepts that characterize digital system behavior are presented using this representation. Finally, an intermediate representation based on Conceptual Dependencies is presented. Its use with a sehantic-based parser to translate from English to the formal representation is illustrated by a series of examples.
IEEE Transactions on Biomedical Circuits and Systems, 2015
Neuromorphic circuits are designed and simulated to emulate the role of astrocytes in phase synch... more Neuromorphic circuits are designed and simulated to emulate the role of astrocytes in phase synchronization of neuronal activity. We emulate, to a first order, the ability of slow inward currents (SICs) evoked by the astrocyte, acting on extrasynaptic N-methyl-D-aspartate receptors (NMDAR) of adjacent neurons, as a mechanism for phase synchronization. We run a simulation test incorporating two small networks of neurons interacting with astrocytic microdomains. These microdomains are designed using a resistive and capacitive ladder network and their interactions occur through pass transistors. Upon enough synaptic activity, the astrocytic microdomains interact with each other, generating SIC events on synapses of adjacent neurons. Since the amplitude of SICs is several orders of magnitude larger compared to synaptic currents, a SIC event drastically enhances the excitatory postsynaptic potential (EPSP) on adjacent neurons simultaneously. This causes neurons to fire synchronously in phase. Phase synchrony holds for a duration of time proportional to the time constant of the SIC decay. Once the SIC decay has completed, the neurons are able to go back to their natural phase difference, inducing desynchronization of their firing of spikes. This paper incorporates some biological aspects observed by recent experiments showing astrocytic influence on neuronal synchronization, and intends to offer a circuit view on the hypothesis of astrocytic role on synchronous activity that could potentially lead to the binding of neuronal information.
Proceedings of the 30th international on Design automation conference - DAC '93, 1993
The power of retiming is often limited by the underlying topology of a computational structure. W... more The power of retiming is often limited by the underlying topology of a computational structure. We combine the power of retiming with a complete set of algebraic transformations in an iterative improvement framework, where retiming and algebraic speed-up algorithms are successively applied, so that the latter enables the former. The key part of the approach is a new algebraic speed-up algorithm being used for the first time in high-level synthesis for transformations of algebraic expressions so that an arbitrary set of input arrival times and output required times are satisfied. Since the new method moves delays forward only and retiming is done locally and very infrequently, it also always calculates the new initial state efficiently. The proposed approach has yielded results better or equal to the best previously published on all benchmark examples and on several novel real-life examples.
Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC '91, 1991
Submicron feature sizes result in designs in which wiring delay is comparable to functional delay... more Submicron feature sizes result in designs in which wiring delay is comparable to functional delay. This paper presents a new approach to the problem of scheduling while simultaneously considering floorplanning. Operators are assigned (and placed) as close as possible to their predecessors in order to minimize the interconnection cost. We also propose an algorithm to reduce interconnection cost by introducing redundant operators. This procedure produces a quite satisfactory result for a practical size example, especially on critical-path dominated cases.
Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC '91, 1991
This paper presents a novel constraint-driven system-level partitioning approach for behavioral s... more This paper presents a novel constraint-driven system-level partitioning approach for behavioral specifications. The software assists a designer in partitioning behavioral specifications onto multiple chips while satisfying hard constraints which include individual chip areas, pin counts, system performance (initiation rate) and system delay. The partitioning method implemented in CHOP is based on predicting the feasibility of tentative partitions by searching through potential implementations of partitions to find combhtations which are feasible while takhtg system integration overhead into account.
Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95, 1995
System level design and behavior transformations have been rapidly establishing themselves as des... more System level design and behavior transformations have been rapidly establishing themselves as design steps with the most inuential impact onnal performance metrics, throughput and latency, o f a design. In this paper we develop a formal ILPbased approach for throughput and latency optimization when algorithm-architecture matching, retiming, and pipelining are considered simultaneously. The effectiveness of the approach is demonstrated on several real-life examples.
Proceedings of the 1989 26th ACM/IEEE conference on Design automation conference - DAC '89, 1989
The ADAM synthesis system consists of two major subsystems: the program tools which synthesize RT... more The ADAM synthesis system consists of two major subsystems: the program tools which synthesize RTL designs from behavioral descriptions and the prediction tools which guide the designer in exploring the design space for a good design. In this paper, we demonstrate the necessity for predictions in narrowing the search space. With the aid of an example, we describe the interaction of a designer with the two subsystems in designing an RTL implementation which maximizes perf0rmanc.e while meeting a given area constraint.
Proceedings of the May 4-7, 1981, national computer conference on - AFIPS '81, 1981
Digital system design has been affected dramatically by verylarge-scale integration (VLSI). Micro... more Digital system design has been affected dramatically by verylarge-scale integration (VLSI). Microprogramming will be affected most greatly by the VLSI design problem. Hardware performing specific functions will be replaced by regular arrays of logic and memory. Design time for VLSI systems will depend on sophisticated design aids for hardware and microcode, and concurrent systems will be common. Microcode will be used in virtually all highly integrated systems.
This paper describes a set of novel tradeoff experiments using MABAL, a Module And Bus ALlocation... more This paper describes a set of novel tradeoff experiments using MABAL, a Module And Bus ALlocation program. MABAL uses a simple heuristic algorithm to concurrently perform functional unit allocation, register allocation, interconnect allocation and module binding, while miniiizing overall cost. MABAL was used to produce over 3000 RTL designs from a specification which had been previously scheduled. 'Ikadeoffs between buses and multiplexers and between data steering logic and functional logic were investigated. The results indicate data path tradeoffs are sensitive to the characteristics of the module library used, and illustrate the difficulty of integrating module generation or logic synthesis with high-level synthesis. This tradeoff study has also highlighted MABAL's capabilities and is unlike any other reported in the literature. This researchwas supported in part by the Defense Advanced Research Project8 Agency and monitored by the OWce of Naval Research under contract No. N00014-87-K-0861 and in part by the Department of Air Force, the Department of Army and the Department of Navy, Contract No. NOOOSCL87-C-0194. support tradeoff studies it should be fast enough to s u p port multiple iterations with designer-imposed decisions and constraints, and should be able to search different parts of the design space with different user constraints.
Uploads
Papers by Alice Parker