Test Chip to Evaluate Measurement Methods for Small Capacitances

IEEE Transactions on Semiconductor Manufacturing, 2003

In this paper, the on-wafer measurement of junction depletion capacitance is examined. This work provides an in-depth discussion of possible probing configurations which can be used. It outlines a method to consistently measure the junction capacitances accurately. The results from this method compare favorably with those extracted using S-parameter measurements. Additionally, methods are formulated to reduce the number of data points required for parameter extraction while at the same time maintaining a high model accuracy.

1990

A technique for measuring low-frequency and low-level capacitance variations is proposed. It is based on a lock-in detection circuit with a feedback loop, containing an integrator and a modulator for zeroing the capacitance mean value. This approach provides a good signal-to-noise ratio and high sensitivity. Capacitance variations can be on the order of 100 p.p.m. of the mean value, and the frequency of the variations can be as low as 0.1 Hz. Stray capacitances and the drift due to the environmental conditions are automatically compensated. The measurement technique, experimental apparatus, and initial results are described. Small variations, about 10 fF, have been measured in the presence of 10-pF mean value.>

Journal of Vacuum …

Scanning probe technology, with its inherent two-dimensionality, offers unique capabilities for the measurement of electrical properties on a nanoscale. We have developed a setup which uses scanning capacitance microscopy (SCM) to obtain electrical information of cross-sectioned samples while simultaneously acquiring conventional topographical atomic force microscopy (AFM) data. In an extension of our work on very large scale integration cross sections, we have now obtained one-dimensional and two-dimensional SCM data of cross sections of blanket-implanted, annealed Si wafers as well as special test structures on Si. We find excellent agreement of total implant depth obtained from SCM signals of these cross-sectioned samples with conventional secondary ion mass spectrometry (SIMS) profiles of the same samples. Although no modeling for a direct correlation between signal output and absolute concentration has yet been attempted, we have inferred quantitative dopant concentrations from correlation to SIMS depth profiles obtained on the same sample. By these means of indirect modeling, we have found that our SCM technique is sensitive to carrier density concentrations varying over several orders of magnitude, i.e., < 1 X 1 0 15 to 1X1020 atoms/cm3, with a lateral resolution of 2 0-1 5 0 nm, depending on tip and dopant level. © 1 9 9 6 A m e r ic a n V acuum Society.

J. of Electrical Engineering, 2017

The development of new fabrication techniques for capacitors with high storage capabilities, called super capacitors, requires appropriated equipment in order to obtain the device's electric behaviours. There is several equipment to perform this analysis operating with alternating or continuum voltage. However, the elevated cost of this equipment makes purchasing it impossible in many laboratories. In this work, we present the development and construction of a low-cost impedance spectrometer that allows for the analysis of the capacitor's electric behaviour without taking too much time. The analysis is performed by alternating voltage and current measurements as a function of the frequency in the range of 0.001 Hz to 100 kHz. The capacitance and electric behaviour of some commercial capacitors are shown in this work, thereby proving the efficiency of the developed equipment.

IEEE Transactions on Circuits and Systems II: Express Briefs, 2016

Reducing the capacitance of programmable capacitor arrays, commonly used in analog integrated circuits, is necessary for low-energy applications. However, limited mismatch data is available for small capacitors. We report mismatch measurement for a 2f F poly-insulator-poly (PIP) capacitor, which is the smallest reported PIP capacitor to the best of the authors' knowledge. Instead of using complicated custom onchip circuitry, direct mismatch measurement is demonstrated and verified using Monte Carlo Simulations and experimental measurements. Capacitive test structures composed of 9 − bit programmable capacitor arrays (PCAs) are implemented in a low-cost 0.35µm CMOS process. Measured data is compared to mismatch of large PIP capacitors, theoretical models, and recently published data. Measurement results indicate an estimated average relative standard deviation of 0.43% for the 2f F unit capacitor, which is better than the reported mismatch of metal-oxide-metal (MOM) fringing capacitors implemented in an advanced 32nm CMOS process.

Microelectronics Journal, 1991

Methods for measuring the intrinsic capacitances of small geometry MOS transistors are described. The influence of short-and narrow-channel effects on the capacitance characteristics of MOS transistors is evaluated. The results are compared with long-channel devices. It is shown that the presented capacitance methods can be used to study the physics of shortchannel transistors.

Journal of Vacuum Science &amp; Technology A: Vacuum, Surfaces, and Films, 1990

Measurement of dopant density in silicon with lateral resolution on the 100 nm scale has been demonstrated with a ‘‘near field’’ capacitance microscope. The technique is based upon the measurement of local capacitance between a 100 nm tip and the sample surface as the tip is scanned over the surface. The capacitive microscope used to image the dopant is capable of measuring capacitance variations of 3×10−22 F/(Hz)1/2, and previously has demonstrated a 25 nm resolution on metallic surfaces. Dopant imaging is achieved by scanning the tip under feedback control close to a silicon surface, and measuring the capacitance variations. Several types of measurements have been made on the submicrometer scale. First, direct two-dimensional visualization of the dopant in silicon has been achieved by this nondestructive, noncontacting technique. Second, capacitance versus voltage (C–V) measurements have been made with high spatial resolution, providing the means for the measurement of many of the...

IEEE Transactions on Electron Devices, 2004

Although scanning capacitance microscopy (SCM) is based on the MOS capacitance theory, the measurement frequency is 915-MHz instead of 100 kHz to 1 MHz in conventional MOS capacitance-voltage measurement. At this high frequency, the reactance of the probe tip-to-substrate capacitance can become smaller than the series resistance of the substrate inversion layer, particularly when the surface mobility is degraded. The response of the oxide-silicon interface traps to SCM measurement is also different due to the use of a 10-kHz signal to determine dC dV. In this paper, we compare experimental and simulation data to demonstrate the effects of interface traps and surface mobility degradation on SCM measurement. Implications on the treatment of SCM data for accurate dopant profile extraction are also presented.

AIP Conference Proceedings, 2003

Although the capability of scanning capacitance microscopy (SCM) for pn junction imaging has been qualitatively demonstrated, quantification of dopant profiles in two-dimensions for pn junctions has proven to be a challenging problem. One reason is that the SCM result is seldom reproducible and this is generally believed to be due to sample preparation technique. In the first part of this work, we made a detailed study of sample preparation methods for SCM measurements. The purpose of the study was to establish an optimum sample preparation technique. Experiments were performed on two known dopant profiles: n type and p type staircase structures with concentration rangng from 10 14 to 10 l9 cm~3. These two samples were cross-sectioned and prepared using different oxidation techniques, which caused variations of interface states and oxide quality. We studied the effect of wet oxidation, thermal oxidation, as well as combined wet and thermal oxidation. Experimental parameters : temperature, baking duration and oxidation methods were studied in detail. To evaluate the oxide quality, we measured the flat band voltage change AV FB by sweeping dC/dV vs. voltage in forward and reverse direction (from accumulation to depletion & vice versa). AVFB represents the amount of the oxide trap charge. Since the staircase structure sample has a large doping range, the contrast reversal effect was obvious. We could minimize this effect by using the optimum experimental condition. In the second part, we investigated samples prepared under this optimum experimental condition.

Nanomaterials

Reference samples are commonly used for the calibration and quantification of nanoscale electrical measurements of capacitances and dielectric constants in scanning microwave microscopy (SMM) and similar techniques. However, the traceability of these calibration samples is not established. In this work, we present a detailed investigation of most possible error sources that affect the uncertainty of capacitance measurements on the reference calibration samples. We establish a comprehensive uncertainty budget leading to a combined uncertainty of 3% in relative value (uncertainty given at one standard deviation) for capacitances ranging from 0.2 fF to 10 fF. This uncertainty level can be achieved even with the use of unshielded probes. We show that the weights of uncertainty sources vary with the values and dimensions of measured capacitances. Our work offers improvements on the classical calibration methods known in SMM and suggests possible new designs of reference standards for cap...