Jia Di

University of Arkansas, Computer Science And Computer Engineering, Faculty Member

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Designing Asynchronous Circuits using NULL Convention Logic (NCL)

Synthesis Lectures on Digital Circuits and Systems, 2009

Delay-Insensitive Ternary Logic

International Conference on Computer Design, 2009

Abstract—This paper develops a delay-insensitive (DI) digital design paradigm that utilizes terna... more Abstract—This paper develops a delay-insensitive (DI) digital design paradigm that utilizes ternary logic as an alternative to dual-rail logic for encoding the DATA and NULL states. This new Delay-Insensitive Ternary Logic (DITL) paradigm is compared with other DI paradigms, such as Pre-Charge Half- Buffers (PCHB) and NULL Convention Logic (NCL), showing that DITL significantly outperforms PCHB and NCL in terms

Ultra-low power delay-insensitive circuit design

Midwest Symposium on Circuits and Systems, 2008

This paper presents a design methodology incorporating multi-threshold CMOS (MTCMOS) into delay-i... more This paper presents a design methodology incorporating multi-threshold CMOS (MTCMOS) into delay-insensitive asynchronous circuits in order to solve the problems of the synchronous counterpart, e.g., sleep signal generation, storage element data loss during sleep mode, and sleep transistor sizing. Significant leakage power reduction has been demonstrated by simulation. Due to the flexible timing requirement feature of delay-insensitive circuits, sub-threshold operation

Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power

Journal of Low Power Electronics, 2008

Ownership Transfer of RFID Tags based on Electronic Fingerprint

by Jia Di and Dale R Thompson

Security and Management, 2008

Pervasive computing devices such as radiofrequency identification (RFID) tags and wearable comput... more Pervasive computing devices such as radiofrequency identification (RFID) tags and wearable computing devices will require ownership transfer. Ownership transfer is a method to transfer a device to a new owner which prevents the previous owner from querying or interacting with the device. It should provide forward security in which no information about the device's past operation or past owner can be derived if the security of the device is compromised in the future. Most proposed ownership transfer techniques are based on changing stored secrets of the device using cryptographic algorithms and authentication protocols. In this work, we propose to transfer ownership by permanently changing the physical attributes of a device to a new but unpredictable value. These physical attributes are like an electronic fingerprint. Results of a proof-of-concept experiment are presented in which one attribute of a RFID tag is changed to a new value thus altering the electronic fingerprint.

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Categorizing RFID Privacy Threats with STRIDE

by Jia Di and Dale R Thompson

Privacy threats by radio frequency identification (RFID) are categorized using the security-orien... more Privacy threats by radio frequency identification (RFID) are categorized using the security-oriented STRIDE model. Categorizing the privacy threats with STRIDE identifies potential strategies for mitigating them. Preliminary results for preventing tracking using universal re-encryption are presented.

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Ultra-Wide Temperature (-230°C to 130°C) DC-Motor Drive with SiGe Asynchronous Controller

by Jia Di and H. Mantooth

2008 IEEE Aerospace Conference, 2008

ABSTRACT Spacecraft routinely experience extreme environmental conditions, including cryogenic (a... more ABSTRACT Spacecraft routinely experience extreme environmental conditions, including cryogenic (as low as -230degC) and elevated temperatures (as high as +130degC). Presently, the temperature of the spacecraft electronics is regulated to its safe operating temperature. The need for temperature regulation on current spacecrafts imposes significant constraints on spacecraft design and also limits performance. This paper details efforts to develop a DC motor drive operational in extreme ambient temperatures (-230 to +130degC). The circuitry of this motor drive is to be based on mature, commercially available technologies and a custom silicon germanium (SiGe) low power asynchronous 8051-pin-compatible microprocessor ASIC. In this paper, the authors present results of passive and active commercial component testing carried out to date, a discussion of the developed automated asynchronous logic design flow, and a discussion of ultra-wide temperature range NULL Convention Logic (NCLtrade) IC design work accomplished to date. Developments made during this research project will allow for a more rapid and more reliable circuit design of ultra-wide range or cryogenic electronics, particularly NCL circuits and power electronic circuits.

Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs

2009 IEEE International Conference on 3D System Integration, 2009

ABSTRACT This paper presents an analysis and comparison between synchronous and delay-insensitive... more ABSTRACT This paper presents an analysis and comparison between synchronous and delay-insensitive asynchronous logic circuits on thermal distributions for investigating novel solutions to the heat dissipation problem in three-dimensional ICs. Due to the spatial and temporal distribution of switching activities in delay-insensitive asynchronous circuits, the thermal density as well as the temperature is largely reduced. Results show that the sample delay-insensitive asynchronous circuit exhibits lower average temperature and more uniform thermal distribution compared to it&#39;s synchronous counterpart.

Glitch-free design for multi-threshold CMOS NCL circuits

Proceedings of the 19th ACM Great Lakes symposium on VLSI - GLSVLSI '09, 2009

ABSTRACT In this paper, a novel design is proposed for eliminating glitches and signal bounces du... more

An efficient modified level set method for brain tissue segmentation

The 2010 IEEE International Conference on Information and Automation, 2010

The paper presents a new efficient method for brain tissue extraction. Firstly, the speed of segm... more The paper presents a new efficient method for brain tissue extraction. Firstly, the speed of segmentation is enhanced through improving classical distance matrix. It can accelerate the distance function convergence faster, and the accuracy is not reduced simultaneously. Secondly, the uniqueness of classical result is changed through the improved method. The evolving lines will be stopped at the same level

A Compact, Self-Contained Cough Monitoring System

2007 IEEE Region 5 Technical Conference, 2007

A self-contained cough monitoring system is a device that allows remote and quantitative cough me... more A self-contained cough monitoring system is a device that allows remote and quantitative cough measurements in patients. The device is being developed to achieve two goals: convenience and security. This paper focuses on the features of the cough monitor hardware and development of the microcontroller firmware, and directions for future research.

A Hardware Threat Modeling Concept for Trustable Integrated Circuits

2007 IEEE Region 5 Technical Conference, 2007

Abstract Similar to the effects of software viruses, hardware can also be compromised by introduc... more

Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems

by Jia Di and Parag Lala

Journal of Electronic Testing, 2007

This paper presents the design, layout, and testability analysis of delay-insensitive circuits on... more This paper presents the design, layout, and testability analysis of delay-insensitive circuits on cellular arrays for nanocomputing system design. In delay-insensitive circuits the delay on a signal path does not affect the correctness of circuit behavior. The combination of delayinsensitive circuit style and cellular arrays is a useful step to implement nanocomputing systems.

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Reversible-Logic Design With Online Testability

by Parag Lala and Jia Di

IEEE Transactions on Instrumentation and Measurement, 2006

Conventional digital circuits dissipate a significant amount of energy because bits of informatio... more Conventional digital circuits dissipate a significant amount of energy because bits of information are erased during the logic operations. Thus, if logic gates are designed such that the information bits are not destroyed, the power consumption can be reduced dramatically. The information bits are not lost in case of a reversible computation. This has led to the development of reversible gates. This paper proposes three new reversible logic gates; two of the proposed gates can be employed to design online testable reversible logic circuits. Furthermore, they can be used to implement any Boolean logic function. The application of the reversible gates in implementing several benchmark functions has been presented.

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Fingerprinting RFID Tags

by Jia Di and Dale R Thompson

IEEE Transactions on Dependable and Secure Computing, 2000

Radio frequency identification (RFID) tags are low-cost devices that are used to uniquely identif... more Radio frequency identification (RFID) tags are low-cost devices that are used to uniquely identify the objects to which they are attached. Due to the low cost and small size that are driving the technology, a tag has limited computational capabilities and resources. These limitations constrain the use of conventional encryption algorithms and security protocols to prevent cloning and counterfeiting of an RFID tag. Therefore, we propose to create an electronic fingerprint of a tag based upon the physical attributes of the tag. We have fingerprinted RFID tags based upon their minimum power responses measured at multiple frequencies. The fingerprint can be used effectively to identify the tags in the future with high probability and to detect counterfeit tags. This mechanism does not increase the cost of the tag and can be applied to any existing tag because it is independent of the computational capabilities and resources of the RFID tag.

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Delay-insensitive asynchronous ALU for cryogenic temperature environments

Midwest Symposium on Circuits and Systems, 2008

This paper details the design and performance of a delay-insensitive asynchronous 8-bit ALU for a... more This paper details the design and performance of a delay-insensitive asynchronous 8-bit ALU for an asynchronous 8051-compliant microcontroller intended for extreme environments. The ALU was designed using a quasi-delay-insensitive logic called NULL Convention Logic (NCL), in order to allow for reliable circuit operation over a wide temperature range and enable extreme supply voltage scaling for low power consumption. The ALU

A COMPARATIVE STUDY OF ULTRA-LOW VOLTAGE DIGITAL CIRCUIT DESIGN

by International journal of VLSI design & Communication Systems (VLSICS) and Jia Di

Ultra-low voltage digital circuit design is an active research area, especially for portable appl... more Ultra-low voltage digital circuit design is an active research area, especially for portable applications such as wearable electronics, intelligent remote sensors, implantable medical devices, and energy-harvesting systems. Due to their application scenarios and circuit components, two major goals for these systems are minimizing energy consumption and improving compatibility with low-voltage power supplies and analog components. The most effective solution to achieve these goals is to reduce the supply voltage, which, however, raises the issue of operability. At ultra-low supply voltages, the integrity of digital signals degrades dramatically due to the indifference between active and leakage currents. In addition, the system timing becomes more unpredictable as the impact of process and supply voltage variations being more significant at lower voltages. This paper presents a comparative study among three techniques for designing digital circuits operating at ultra-low voltages, i.e., Schmitt-triggered gate structure, delayinsensitive asynchronous logic, and Fully-Depleted Silicon-on-Insulator technology. Results show that despite the tradeoffs, all eight combinations of these techniques are viable for designing ultra-low voltage circuits. For a given application, the optimum circuit design can be selected from these combinations based on the lowest voltage, the dynamic range, the power budget, the performance requirement, and the available semiconductor process node.

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