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Reversible-Logic Design with Online Testability
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Electrical and Electronic Engineering

Reversible-Logic Design With Online Testability

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2006, IEEE Transactions on Instrumentation and Measurement

https://doi.org/10.1109/TIM.2006.870319
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Abstract

Conventional digital circuits dissipate a significant amount of energy because bits of information are erased during the logic operations. Thus, if logic gates are designed such that the information bits are not destroyed, the power consumption can be reduced dramatically. The information bits are not lost in case of a reversible computation. This has led to the development of reversible gates. This paper proposes three new reversible logic gates; two of the proposed gates can be employed to design online testable reversible logic circuits. Furthermore, they can be used to implement any Boolean logic function. The application of the reversible gates in implementing several benchmark functions has been presented.

Figures (13)
TRUTH TABLE OF THE FREDKIN GATE outputs. Some of the major problems with reversible-logic synthesis are [4]:
TRUTH TABLE OF THE FREDKIN GATE outputs. Some of the major problems with reversible-logic synthesis are [4]:
TRUTH TABLE OF THE PROPOSED REVERSIBLE-LOGIC GATE
TRUTH TABLE OF THE PROPOSED REVERSIBLE-LOGIC GATE
Fig. 3. (a) New reversible-logic gate R. (b) Signal duplication. (c) AND gate. (d) NAND gate. (e) OR gate
Fig. 3. (a) New reversible-logic gate R. (b) Signal duplication. (c) AND gate. (d) NAND gate. (e) OR gate
Fig. 4. (a) Reversible-logic gate R1 and reversible-logic gate R2. (b) OR and EXOR gates. (c) XNOR and NAND gates. (d) NOR gate. (e) AND gate
Fig. 4. (a) Reversible-logic gate R1 and reversible-logic gate R2. (b) OR and EXOR gates. (c) XNOR and NAND gates. (d) NOR gate. (e) AND gate
Fig. 5. Testable block. [Fig. 4(b)]. The EXNOR function and the NAND function are obtained by setting input c to 1 [Fig. 4(c)]. The NOR function can be obtained by cascading two R1 gates [Fig. 4(d)]. An AND gate also requires the cascading of two gates [Fig. 4(e)]. R1 can transfer a signal at input a to output wu by setting the input c to 0. can be obtained by cascading two R1 gates [Fig. 4(d)]. An
Fig. 5. Testable block. [Fig. 4(b)]. The EXNOR function and the NAND function are obtained by setting input c to 1 [Fig. 4(c)]. The NOR function can be obtained by cascading two R1 gates [Fig. 4(d)]. An AND gate also requires the cascading of two gates [Fig. 4(e)]. R1 can transfer a signal at input a to output wu by setting the input c to 0. can be obtained by cascading two R1 gates [Fig. 4(d)]. An
Fig. 7. Testable block embedded with the two-pair two-rail checker. Fig. 6. Two-pair two-rail checker.
Fig. 7. Testable block embedded with the two-pair two-rail checker. Fig. 6. Two-pair two-rail checker.
The NAND block-based implementation of function 'F”’ = ab + cd is given below:
The NAND block-based implementation of function 'F”’ = ab + cd is given below:
Fig. 9. Reversible NAND block implementation for the function ab + cd. implemented using 12 transistors. The implementation of gate F1 is shown in Fig. 12. It took 26 transistors to implement the design. Fig. 13 shows the four inputs and one output of the
Fig. 9. Reversible NAND block implementation for the function ab + cd. implemented using 12 transistors. The implementation of gate F1 is shown in Fig. 12. It took 26 transistors to implement the design. Fig. 13 shows the four inputs and one output of the
reversible gate R2. As the first three output of the gate are just the direct wire connection from input, the input d, e, and f of the gate can be used as the output.
reversible gate R2. As the first three output of the gate are just the direct wire connection from input, the input d, e, and f of the gate can be used as the output.
COMPARISON OF THE PROPOSED GATES WITH FREDKIN AND TOFFOLI GATES in Table VIII. The percentage overhead of the realized design: ranges from 12.5 to 33.28%. power analysis has been made using Xilinx ISE version 6.1 [11]. The full adder with propagate was implemented at the behavioral level [VHSIC (very high speed integrated circuit) hardware description language (VHDL)] using the Fredkin gate, the proposed gates, and the Toffoli gate. Table VI shows the comparison of the designs using these gates. The implemen- tation of the adder circuit is given in [15].
COMPARISON OF THE PROPOSED GATES WITH FREDKIN AND TOFFOLI GATES in Table VIII. The percentage overhead of the realized design: ranges from 12.5 to 33.28%. power analysis has been made using Xilinx ISE version 6.1 [11]. The full adder with propagate was implemented at the behavioral level [VHSIC (very high speed integrated circuit) hardware description language (VHDL)] using the Fredkin gate, the proposed gates, and the Toffoli gate. Table VI shows the comparison of the designs using these gates. The implemen- tation of the adder circuit is given in [15].

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