Papers by Marek Perkowski
Logic Synthesis for a Regular Layout
VLSI Design, 1999
VLSI Design, 2002
A compact data representation, in which the typically required operations are performed rapidly, ... more A compact data representation, in which the typically required operations are performed rapidly, and effective and efficient algorithms that work on these representations are the essential elements of a successful CAD tool. The objective of this paper is to present a new data representation-term trees (TTs)-and to discuss its application for an effective and efficient structural automatic test-pattern generation (ATPG). Term trees are decision diagrams similar to BDDs that are particularly suitable for structure representation of AND -OR and AND -EXOR circuits. In the paper, a flexible algorithm for minimum term-tree construction is discussed and an effective and efficient algorithm for ATPG for AND-EXOR and AND -OR circuits is proposed.
Efficient Algorithms for Creation of Linearly-independent Decision Diagrams and their Mapping to Regular Layouts
VLSI Design, 2002
Generalized Inclusive Forms—New Canonical Reed-Muller Forms Including Minimum ESOPs
VLSI Design, 2002
A SURVEY OF LITERATURE ON FUNCTION DECOMPOSITION VERSION IV November 20, 1995
Page 1. A SURVEY OF LITERATURE ON FUNCTION DECOMPOSITION VERSION IV November 20, 1995 Marek A. Pe... more Page 1. A SURVEY OF LITERATURE ON FUNCTION DECOMPOSITION VERSION IV November 20, 1995 Marek A. Perkowski, Stanislaw Grygiel, and the Functional Decomposition Group, Department of Electrical Engineering ...
Algebraic Characterization of Reversible Logic Gates
Theory of Computing Systems, 2006
Abstract Reversible logic plays an important role in quantum computing. This paper investigates t... more Abstract Reversible logic plays an important role in quantum computing. This paper investigates the universality and composition power of various known and new reversible gates. We present the algebraic characterization of selected new families of Boolean ...
Theoretical Computer Science, 2005
Reversible logic plays an important role in application of adiabatic low power CMOS computing and... more Reversible logic plays an important role in application of adiabatic low power CMOS computing and quantum computing. In this paper we introduce families of reversible gates based on majority and we prove their properties in reversible circuit synthesis. These gates can be used to synthesize reversible circuits of minimum "scratchpad register width" for arbitrary reversible functions. We show that, given a majority Boolean function f with 2k+1 inputs, f can be implemented by a reversible logic gate with 2k+1 inputs and 2k+1 outputs, i.e., without any constant inputs. The problem is formulated in terms of group theory and solved by using the algebraic software GAP for logic synthesis.
Theoretical Computer Science, 2006
Recent research in generalizing quantum computation from 2-valued qudits to dvalued qudits has sh... more Recent research in generalizing quantum computation from 2-valued qudits to dvalued qudits has shown practical advantages for scaling up a quantum computer. A further generalization leads to quantum computing with hybrid qudits where two or more qudits have different finite dimensions. Advantages of hybrid and dvalued gates (circuits) and their physical realizations have been studied in detail by cases, a quantum computation is performed when a unitary evolution operator, acting as a quantum logic gate, transforms the state of qudits in a quantum system. Unitary operators can be represented by square unitary matrices. If the system consists of a single qudit, then Tilma et al (J. Phys. A: Math. Gen. 35 (2002) 10467-10501) have shown that the unitary evolution matrix (gate) can be synthesized in terms of its Euler angle parametrization. However, if the quantum system consists of multiple qudits, then a gate may be synthesized by matrix decomposition techniques such as QR factorization and the Cosine-sine Decomposition (CSD). In this article, we present a CSD based synthesis method for n qudit hybrid quantum gates, and as a consequence, derive a CSD based synthesis method for n qudit gates where all the qudits have the same dimension.
Theoretical Computer Science, 2011
Reversible circuits play an important role in quantum computing. This paper studies the realizati... more Reversible circuits play an important role in quantum computing. This paper studies the realization problem of reversible circuits. For any n-bit reversible function, we present a constructive synthesis algorithm. Given any n-bit reversible function, there are N distinct input patterns different from their corresponding outputs, where N ≤ 2 n , and the other (2 n − N) input patterns will be the same as their outputs. We show that this circuit can be synthesized by at most 2n · N '(n − 1)'-CNOT gates and 4n 2 · N NOT gates. The time and space complexities of the algorithm are Ω(n · 4 n ) and Ω(n · 2 n ), respectively. The computational complexity of our synthesis algorithm is exponentially lower than that of breadth-first search based synthesis algorithms.
Theoretical Computer Science, 2008
Erratum to: "Synthesis of multi-qudit hybrid and d-valued quantum logic circuits by decomposition... more Erratum to: "Synthesis of multi-qudit hybrid and d-valued quantum logic circuits by decomposition" [Theoret.
The Computer Journal, 2007
Reversible circuits play an important role in quantum computing, which is one of the most promisi... more Reversible circuits play an important role in quantum computing, which is one of the most promising emerging technologies. In this paper, we investigate the problem of optimally synthesizing 4-bit reversible circuits. We present an enhanced bi-directional synthesis approach. Owing to the exponential nature of the memory and run-time complexity, all existing methods can only perform four steps for the Controlled-Not gate NOT gate, and Peres gate library. Our novel method can achieve 12 steps. As a result, we augment the number of circuits that can optimally be synthesized by over 5 3 10 6 times. We synthesized 1000 random 4-bit reversible circuits. The statistical analysis result supports our estimation. The quantum cost of our result is also better than the quantum cost of other approaches. The promising experimental results demonstrate the effectiveness of our approach.
Learning in Hardware: Architecture and Implementation of an FPGA-Based Rough Set Machine
The “Learning Hardware” approach proposed here involves creating a computational network based on... more The “Learning Hardware” approach proposed here involves creating a computational network based on feedback from the environment (for instance, positive and negative examples from the trainer), and realizing this network in an array of Field Programmable Gate Arrays (FPGAs). We advocate the approaches based on a “strong AI criterion”; for instance, the computational networks can be built based on Sum-of-Products logic minimization, functional logic decomposition, or Decision Tree construction. Here we propose the constructive induction approach to Learning Hardware based on Rough Sets Theory (RST). This approach allows the use of logical analysis to develop efficient hardware-realizable algorithms, and is contrasted with the popular Evolvable Hardware (EHW) approach in which learning/evolution is based on the genetic algorithm only. The RST algorithms have a natural high parallelism and high possible speed-ups. Using a fast prototyping tool, the DEC-PERLE-1 board based on an array of...
Fast Minimization Of Multi-Output Boolean Functions In Sum-Of-Condition-Decoders Structures
A CDEC gate, or a condition decoder, being a product of an AND and NAND of literals, has been int... more A CDEC gate, or a condition decoder, being a product of an AND and NAND of literals, has been introduced in the logic array of the high-speed EPLD CY7C361 chip from Cypress. We give an algorithm for the minimization of SUM-OF-CDEC (SOC) expressions. This algorithm produced the minimum solutions on all small single-output functions, as required by this chip. We
Logic synthesis for regular fabric realized in quantum dot cellular automata
Extended superposed quantum-state initialization using disjoint prime implicants
Physical Review A, 2009
Extended superposed quantum-state initialization using disjoint prime implicants is an algorithm ... more Extended superposed quantum-state initialization using disjoint prime implicants is an algorithm for generating quantum arrays for the purpose of initializing a desired quantum superposition. The quantum arrays generated by this algorithm almost always use fewer ...
Integrated circuits with a highly regular, repeated structure outperform IC's with complex l... more Integrated circuits with a highly regular, repeated structure outperform IC's with complex logic interconnects, in transistor density, gate delay time, and testability. They will be even more important for future technologies such as single electron transistors. These advantages drive the search for highly regular structures that can be used to replace complex logic. This paper studies synthesis and test of regular lattice structures built of Davio gates. Tools useful for analysis and synthesis of the triangular logic lattice structures are given. Finally, universal tests for the structures are developed.
a canonical and/exor form that includes both the
Kybernetes, 2004
Two methods of decomposition of probabilistic relations are presented. They consist of splitting ... more Two methods of decomposition of probabilistic relations are presented. They consist of splitting relations (blocks) into pairs of smaller blocks related to each other by new variables generated in such a way as to minimize a cost function which depends on the size and structure of the result. The decomposition is repeated iteratively until a stopping criterion is met. Topology and contents of the resulting structure develop dynamically in the decomposition process and reflect relationships hidden in the data.
Kybernetes, 2004
Modified Reconstructability Analysis (MRA), a novel decomposition technique within the framework ... more Modified Reconstructability Analysis (MRA), a novel decomposition technique within the framework of set-theoretic (crisp possibilistic) Reconstructability Analysis, is applied to 3-variable NPN-classified Boolean functions. MRA is superior to conventional Reconstructability Analysis (CRA), i.e. it decomposes more NPN functions. MRA is compared to Ashenhurst-Curtis (AC) decomposition using two different complexity measures: log-functionality, a measure suitable for machine learning, and the count of the total number of two-input gates, a measure suitable for circuit design. MRA is superior to AC using the first of these measures, and is comparable to, but different from AC, using the second.
Free Kronecker decision diagrams and their application to Atmel 6000 series FPGA mapping
European Design and Test Conference, 1994
This paper introduces the concepts of Pseudo- Kronecker Decision Diagrams (PKDDs) with Negated Ed... more This paper introduces the concepts of Pseudo- Kronecker Decision Diagrams (PKDDs) with Negated Edges, as well as F+ee Kronecker Decision Diagrams (FKDDs), that generalize both the well-known Bi- nary Decision Diagmms and Functional Decision Di- agmms, as well as Ihe recently introduced Ordered Kronecker Decision Diagrams (OKDDs . We give efficient algorithm for Ihe generation / o FKDDs for multi-output
Uploads
Papers by Marek Perkowski