CN107658315A - Semiconductor device and preparation method thereof - Google Patents

Abstract

The present invention relates to a kind of nand memory and preparation method thereof, nand memory includes：Silicon substrate；Multiple peripheral components；The multiple NAND strings formed above the peripheral components；The monocrystalline silicon layer formed above the multiple NAND string, the monocrystalline silicon layer contact connection, and the interconnection layer of one or more first formed between the multiple peripheral components and multiple NAND strings with the multiple NAND string.The present invention is by the way that the making of array device and peripheral components is separated, can be avoided interacting during the manufacture of two devices the manufacturing process of other side, therefore solve the problems, such as the making of layer behind in the prior art made by layer above after temperature limiting, so as to obtain good peripheral components performance.It is superimposed upon additionally, due to array device on peripheral components, realizes high device density.

Description

Semiconductor device and manufacturing method thereof

technical field

The invention relates to a NAND memory and a preparation method thereof, in particular to a NAND memory forming a 3D NAND flash memory and a preparation method thereof.

Background technique

With the continued emphasis on highly integrated electronics, there is a continuing need for semiconductor memory devices that operate at higher speeds and lower power and have increased device densities. To this end, devices with smaller dimensions and multilayer devices with transistor cells arranged in horizontal and vertical arrays have been developed. 3D NAND is an emerging type of flash memory developed by the industry. It solves the limitations of 2D or planar NAND flash memory by stacking memory particles together.

The planar structure of NAND flash memory is approaching its actual expansion limit, which brings severe challenges to the semiconductor memory industry. The new 3D NAND technology stacks multiple layers of data storage cells vertically with excellent precision. Based on this technology, storage devices with a storage capacity several times higher than similar NAND technologies can be created. The technology enables higher storage capacity in a smaller footprint, resulting in significant cost savings, reduced power consumption, and dramatic performance gains for many consumer mobile devices and the most demanding enterprise deployments demand.

In one approach, planar memory cells (eg, NAND memory cells) are formed in a conventional horizontal array. Multiple horizontal arrays are then stacked vertically. Limitations associated with this approach include low reliability in the resulting devices and difficulty in achieving 16nm fabrication by lithography due to the critical lithographic steps required for each layer in achieving the smallest feature size, making it difficult to further improve storage. Furthermore, in this configuration, the size of the drive transistors used to drive the control select gates is a function of the number of layers; therefore, the size of the drive transistors is a multiple of the number of layers. This can lead to integration issues and thermal issues. In another approach, multi-layer memories with vertically oriented channels have been developed. In one configuration, a plurality of select gate layers are formed on the substrate through which a vertical channel passes. In each vertical channel, a lower select gate layer is configured to function as a lower select gate, a plurality of intermediate gate layers are configured to function as control gates, and an upper select gate layer is configured to function as an upper select gate ( upper select gate). The upper select gates adjacent to each other in the first horizontal direction are connected to serve as row select lines of the device. The vertical channels adjacent to each other in the second horizontal direction are connected to serve as bit lines of the device. Other attempts to vertically align channels have had limited success.

At present, regarding 3D NAND flash memory technology, there have been extensive patent applications at home and abroad. For example, the Chinese invention patent application publication number CN101483194A discloses a vertical non-volatile memory device and a manufacturing method thereof. In the semiconductor device and its manufacturing method, the device includes a substrate of single crystal semiconductor material extending in the horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of select gate patterns are provided, each select gate pattern between an adjacent lower interlayer dielectric layer and an adjacent upper interlayer dielectric layer. A vertical channel of semiconductor material extends vertically through a plurality of interlayer dielectric layers and selection gate patterns, and a selection gate insulating layer is between each selection gate pattern and the vertical channel and insulates the selection gate pattern from the vertical channel. As shown in FIG. 1 , it is a cross-sectional view of the vertical channel memory device. In the vertical channel memory device, a Si substrate layer 300, a peripheral circuit region 302, and an array device layer are sequentially formed from bottom to top.

However, the disadvantage of the above-mentioned patented technology is that the above-mentioned vertical channel memory device is sequentially fabricated on only one Si substrate layer, so that the temperature of subsequent devices (such as NAND strings) must be limited during fabrication, otherwise it will be damaged due to excessive temperature. This leads to ion diffusion of ions in the ion implantation layer of previously fabricated devices (such as NMOS and PMOS devices fabricated on silicon substrates), making it difficult to control the bonding depth between devices, thus affecting product performance. That is to say, the manufacturing requirements between the various layers will be limited to each other.

In addition, after the peripheral device 302 is fabricated on the silicon substrate in the above patent, a NAND device is formed on top of the peripheral device 302 . As such, the NAND devices are isolated from the silicon substrate. Such NAND devices need to use a source layer instead of the silicon substrate, resulting in reduced device performance.

How to avoid the interaction between layers in the manufacturing process and ensure the performance of the product is a problem that needs to be solved at present.

Contents of the invention

The purpose of the present invention is achieved through the following technical solutions.

In view of the above existing problems, the present invention discloses a semiconductor device, which comprises from bottom to top: a silicon substrate, peripheral devices formed on the silicon substrate, and one or more interconnections formed on the peripheral devices layers and array devices formed on one or more interconnect layers. In some embodiments, the array device further includes a single crystal silicon layer formed on the upper end of the array device.

In some embodiments, the semiconductor device further includes a plurality of back-end-of-line (BEOL) interconnect layers and pad layers formed over the array device.

In some embodiments, the peripheral devices include a plurality of metal oxide semiconductor field effect transistors (MOSFETs). In some embodiments, the peripheral devices are formed on a silicon substrate. In some embodiments, the silicon substrate has doped regions and isolation regions. In some embodiments, the metal oxide semiconductor field effect transistors (MOSFETs) of the peripheral devices are used as different functional devices of the memory, such as page buffers, sense amplifiers, column decoders or row decoders.

In some embodiments, the one or more interconnect layers include peripheral interconnects; in some embodiments, the peripheral interconnects include multiple interconnect layers and contact layers. In some embodiments, the interconnect layer includes a plurality of metal layers. The metal layer can be made of tungsten, copper, aluminum or other suitable materials. In some embodiments, the contact layer may be made of tungsten, copper, aluminum or other suitable materials. In some embodiments, the one or more interconnection layers are formed to transfer electrical signals between different peripheral transistors, or transfer electrical signals between peripheral transistors and array devices.

In some embodiments, one or more interconnect layers include array interconnects. In some embodiments, the array interconnect includes a plurality of interconnect layers and contact layers. In some embodiments, the interconnect layer includes a plurality of metal layers. The metal layer can be made of tungsten, copper, aluminum or other suitable materials. In some embodiments, the contact layer may be made of tungsten, copper, aluminum or other suitable materials. In some embodiments, the peripheral interconnection is formed to transfer electrical signals between different regions of the array device, or transfer electrical signals between peripheral transistors and the array device.

In some embodiments, the array device includes a plurality of NAND strings. In some embodiments, the array device further includes a plurality of interconnection layers formed under the plurality of NAND strings. In some embodiments, the array device further includes a single crystal silicon layer formed over the NAND strings. In some embodiments, the monocrystalline silicon layer is part of a silicon substrate and is thinned by suitable techniques in subsequent processes, such as backgrinding, wet/dry etching, and/or chemical mechanical polishing techniques. In some embodiments, the monocrystalline silicon layer is in contact with the plurality of NAND strings. In some embodiments, the thickness of the monocrystalline silicon layer is between 200 nanometers and 50 micrometers. In some embodiments, the thickness of the monocrystalline silicon layer is between 500 nm and 10 microns. In some embodiments, the thickness of the monocrystalline silicon layer is between 500 nm and 5 microns. In some embodiments, the monocrystalline silicon layer is partially or fully doped with n-type and/or p-type dopants.

In some embodiments, each of said NAND strings includes a semiconductor channel (eg, a silicon channel) extending in a vertical direction through said plurality of conductor/insulator stacks. Each such layer of conductor or insulator may be referred to as a hierarchical layer. Multiple conductor/insulator stacks may also be referred to as a hierarchical layer stack. The conductor layers can be used as word lines (or control gates). Multiple layers may be located between the conductor layer and the semiconductor channel. In some embodiments, the plurality of layers includes a tunnel layer, eg, a tunnel oxide layer, through which electrons or holes in the semiconductor channel can tunnel into the charged storage cell layer of the NAND string. In some embodiments, the plurality of layers includes a layer of memory cells capable of storing charge. The storage or removal of charge in the memory cell layer determines the on/off state of the semiconductor channel. In some embodiments, the memory cell layer may be made of a polysilicon layer or a silicon nitride layer. In some embodiments, the plurality of layers further includes a barrier layer, such as a silicon oxide layer or a composite layer consisting of silicon oxide/silicon nitride/silicon oxide (ONO) triple layers. In some embodiments, the barrier layer may further include a high-K dielectric layer (eg, alumina).

In some embodiments, the NAND string further includes an epitaxial silicon layer formed on top of the semiconductor channel. In some embodiments, the epitaxial silicon layer is grown epitaxially from a single crystal silicon layer over the NAND string.

In some embodiments, the NAND string further includes select gates formed from one or more upper conductor layers in the hierarchical layer stack. In some embodiments, the select gate controls on/off states of semiconductor channels of the NAND string. In some embodiments, the select gates of the NAND strings are formed by a separate conductor layer above the hierarchical layer stack. In some embodiments, the NAND string further includes select gates formed from one or more lower conductor layers in the hierarchical layer stack. In some embodiments, the select gates of the NAND strings are formed by a separate conductor layer below the hierarchical layer stack.

In some embodiments, the NAND strings are connected to source contacts through doped regions of the monocrystalline silicon layer formed over the NAND strings. In some embodiments, the doped region of the monocrystalline silicon layer is doped with a p-type dopant. In some embodiments, the source contact extends vertically through the hierarchical layer stack and contacts the monocrystalline silicon layer at an upper end. In some embodiments, the bottom end of the source contact is in contact with one or more contacts formed below the source contact.

In some embodiments, the array device further includes a plurality of word line contacts. In some embodiments, the plurality of word line contacts extend vertically and each of the plurality of word line contacts has an end in contact with the word line, whereby the word line of the array device can pass through the word line contact. Points are addressed individually. In some embodiments, each wordline contact is formed below and connected to the wordline. In some embodiments, the plurality of word line contacts are formed by wet etching or dry etching to form contact holes or contact grooves, and then a conductor (such as tungsten) is used to fill the contact hole holes or contact grooves. In some embodiments, filling the contact hole or contact trench includes depositing a barrier layer and/or an adhesion layer prior to depositing the conductor. In some embodiments, the wordline contacts are first formed above the wordlines, and then the wafer is turned upside down so that the wordline contacts are below the wordlines.

In some embodiments, the interconnect layer formed below the NAND strings includes a plurality of bit line contacts that make contact with the bottom of the NAND strings. In some embodiments, the contact holes of the plurality of bit line contacts are independent from each other. In some embodiments, the bit line contacts connect each NAND string such that each NAND string can be independently addressed by the contacts. In some embodiments, the bit line contacts are formed as follows: first, contact holes or contact trenches are formed by wet etching or dry etching, and then the contact holes or contact trenches are filled with a conductor (such as tungsten). groove. In some embodiments, the filling of the contact holes or contact trenches is accomplished using chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In some embodiments, the bitline contacts are first formed over the NAND strings, and then the wafer is turned upside down so that the bitline contacts are under the NAND strings.

In some embodiments, one or more interconnect layers further include a bonding interface. In some embodiments, the bonding interface may be formed between two insulating layers, such as between a silicon nitride layer and a silicon oxide layer. The bonding interface may also be formed between two metal layers, for example one copper layer and another copper layer. In some embodiments, the bonding interface may include an interface between insulating layers or an interface between metal layers. In some embodiments, the bonding interface is formed by chemical bonding between insulating and/or conductive layers on both sides of the bonding interface. In some embodiments, the bonding interface is formed by physical interaction (eg, interdiffusion) between insulating and/or conductive layers on either side of the bonding interface. In some embodiments, before the bonding process, the bonding interface is formed by performing plasma treatment on the surfaces on both sides of the bonding interface. In some embodiments, before the bonding process, the bonding interface is formed by heat-treating the surfaces on both sides of the bonding interface.

In some embodiments, the memory further includes a plurality of hierarchical layer stacks. In some embodiments, intermediate stack layers may be formed between adjacent hierarchical layer stacks. In some embodiments, the middle stack layer connects the NAND strings of the upper hierarchical layer stack and the NAND strings of the lower hierarchical layer stack. In some embodiments, the NAND strings of the upper level stack and the NAND strings of the lower level stack are electrically connected through conductor portions of the middle stack layer to form longer NAND strings.

In some embodiments, the apparatus further includes the plurality of through-array contacts extending vertically through the level stack or stacks. In some embodiments, the plurality of through-array contacts connects both interconnect layers formed below the NAND strings of the hierarchical layer stack and interconnect layers formed above the NAND strings of the hierarchical layer stack. In some embodiments, the plurality of through-array contacts are formed by first forming contact holes and/or contact trenches by dry etching, and then filling the contact holes and/or contact trenches with a conductive material (such as tungsten, copper, or silicide). contact holes or contact trenches.

In some embodiments, the formed BEOL interconnection layer is used to transmit electrical signals of semiconductor devices, including electrical signals of array devices and peripheral devices. In some embodiments, the formed liner layer is used to transmit electrical signals of the semiconductor device to external electrical signal channels. In some embodiments, the BEOL interconnect layer includes an interconnect conductor layer and a contact layer. The interconnect conductor layers and contact layers include conductive materials such as tungsten, copper, aluminum, silicide, and/or other suitable conductive materials. In some embodiments, the substrate layer includes a conductor, such as tungsten, copper, aluminum, silicide, and/or other suitable conductive materials.

In view of the above problems, the present invention also discloses a method for manufacturing a semiconductor device. Wherein, the method for preparing a semiconductor device comprises the steps of:

Form peripheral devices;

forming an array device;

Arranging the peripheral device and the array device oppositely and bonding the peripheral device and the array device through an adhesive interface.

Preferably, wherein, preparing the peripheral device specifically includes the following steps:

forming a first silicon substrate;

forming peripheral devices on the first silicon substrate, wherein the peripheral devices include MOS transistors;

Peripheral interconnects are formed over the peripheral devices.

Preferably, wherein, preparing the array device specifically includes the following steps:

forming a second silicon substrate;

forming a doped region and an isolation region in the second silicon substrate;

One or more NAND strings are formed on the second silicon substrate; wherein each of the NAND strings includes: a plurality of conductor/insulator stacks extending vertically through the plurality of conductor/insulator stacks a layer of semiconductor channels, a plurality of memory cells formed between the semiconductor channels and the conductor layer, a tunnel layer formed between the memory cells and the semiconductor channel, a barrier layer formed between the memory cells and the conductor layer, and a monocrystalline silicon epitaxial layer formed at the bottom of the semiconductor channel; wherein the one or more NAND strings are in contact with the second silicon substrate. In some embodiments, the monocrystalline silicon epitaxial layer is epitaxially grown from the second silicon substrate; wherein the one or more NAND strings further include a select gate formed at one end of the NAND string.

An array interconnection layer is formed on the NAND strings, wherein the step of forming the array interconnection layer includes forming bit line contacts to contact one or more NAND strings. Forming the array interconnection layer further includes forming one or more interconnection and contact layers, wherein the interconnection and contact layers include conductive materials such as tungsten, aluminum, copper, and/or other suitable materials.

According to some embodiments, forming the array interconnect layer further includes forming source contacts for one or more NAND strings. In some embodiments, the source contact extends vertically through multiple conductor/insulator stacks. In some embodiments, one end of the source contact is in contact with the second silicon substrate, and the other end is in contact with the interconnection layer of the array contacts. In some embodiments, the source contact is electrically connected to one or more NAND strings through the second silicon substrate.

The bonding step specifically includes: arranging the peripheral device and the array device oppositely and bonding them through the bonding interface, then thinning the back side of the second silicon substrate layer, forming a Pad layer on the back side, and A BEOL dielectric layer is formed on the PAD layer.

Combine the peripheral device and the array device at the bonding interface, wherein the step of combining the peripheral device and the array device includes: turning the array device upside down, aligning the array interconnection layer facing the peripheral device and the peripheral interconnection layer facing the array device, and The array device is placed on the peripheral device such that the surface of the array interconnection layer contacts the surface of the peripheral interconnection layer, and a bonding process is performed to form an adhesive interface. In some embodiments, the bonding treatment includes a plasma treatment process, a wet process and/or a heat treatment process, so that the surface of the array interconnection layer facing the bonding interface and the surface of the peripheral interconnection layer form a physical or chemical bond. In some embodiments, the surface of the array interconnect layer includes a silicon nitride layer and the surface of the peripheral interconnect layer includes a silicon oxide layer. In some embodiments, the surface of the array interconnect layer includes a silicon oxide layer and the surface of the peripheral interconnect layer includes a silicon nitride layer. In some embodiments, both the surface conductors of the array interconnect layer and the surface conductors of the peripheral interconnect layer include copper.

In some embodiments, the combination of the surface of the array interconnection layer and the peripheral interconnection layer is achieved by forming physical interactions (such as interdiffusion) between insulating layers (such as silicon nitride layers or silicon oxide layers) and/or conductor layers on both sides. )Completed. The interface between the array interconnect layer and the surface of the peripheral interconnect layer is a bonding interface. In some embodiments, prior to the bonding process, plasma treatment of the surfaces of the array interconnect layer and the peripheral interconnect layer can enhance the bonding force between the two surfaces. In some embodiments, prior to the bonding process, wet processing of the surfaces of the array interconnection layer and the peripheral interconnection layer can strengthen the bonding force between the two surfaces. In some embodiments, placing the array interconnect layer over the peripheral interconnect layer includes aligning the contact areas of the array interconnect layer and the peripheral interconnect layer so that the contact areas of the two interconnect layers make contact when the two sides are brought together. In some embodiments, the heat treatment operation is performed while the surfaces of the array interconnect layer and the peripheral interconnect layer are in contact. In some embodiments, this thermal treatment promotes interdiffusion between the conductive material (eg, copper) of the array interconnect layer and the peripheral interconnect layer.

In some embodiments, one or more bonding interfaces may be formed during the manufacturing method. In some embodiments, multiple array devices are combined with one peripheral device. In some embodiments, an array device can be combined with multiple peripheral devices. In some embodiments, multiple array devices are combined with multiple peripheral devices.

In some embodiments, the array device includes multiple hierarchical layer stacks. Each hierarchical layer stack includes multiple conductor/insulation layers. In some embodiments, intermediate stack layers may be formed between adjacent hierarchical layer stacks. In some embodiments, the middle stack layer connects the NAND strings of the upper hierarchical layer stack and the NAND strings of the lower hierarchical layer stack.

After combining the array device and the peripheral device, the second silicon substrate of the array device is thinned. In some embodiments, the process of thinning the second silicon substrate is accomplished by a chemical mechanical planarization (CMP) process. In some embodiments, the process of thinning the second silicon substrate may also be completed by other suitable processes, for example, wet etching and/or dry etching.

Since the array device and the peripheral device are formed independently, the process sequence of forming the array device/array interconnection layer and the peripheral device/peripheral interconnection layer can be interchanged.

The advantages of the present invention are:

The present invention separates the manufacture of the array device and the peripheral device on two silicon wafers, which can prevent the two devices from affecting each other's manufacturing process during manufacture, thus solving the problem that the manufacturing of the latter layer is affected by the front layer in the prior art. The problem of temperature limit after production.

In the semiconductor device disclosed in the present invention, the density of the device is increased by arranging the array device layer on the top of the peripheral circuit layer. Moreover, the preparation method of the peripheral circuit layer and the array device layer is simplified, thereby obtaining better performance of the peripheral circuit layer (for example, CMOS performance). The improvement of CMOS performance is due to the separate preparation of peripheral circuits and array devices, so that the high-temperature process of rear-end array devices has no effect on front-end peripheral devices, and the performance of back-end devices can be improved (for example, there will be no additional diffusion of dopants, such as The junction depth formed by ion implantation can be better controlled, etc.)

Description of drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiment. The drawings are only for the purpose of illustrating a preferred embodiment and are not to be considered as limiting the invention. Also throughout the drawings, the same reference numerals are used to designate the same components. In the attached picture:

FIG. 1 is a cross-sectional view of a conventional vertical channel memory device.

Fig. 2 is a schematic structural diagram of a NAND memory according to an embodiment of the present invention;

3A-3D are schematic diagrams of manufacturing steps of peripheral devices of a NAND memory according to an embodiment of the present invention;

4A-4D are schematic diagrams of manufacturing steps of an array device of a NAND memory according to an embodiment of the present invention;

5A-5C are schematic diagrams of manufacturing steps of a NAND memory obtained by bonding an array device and a peripheral device according to an embodiment of the present invention.

FIG. 6 is a flowchart of an example method 600 of forming peripheral devices and peripheral interconnect layers.

FIG. 7 is a flowchart of an example method 700 of forming array devices and array interconnect layers.

FIG. 8 is a flowchart of an example method 800 of combining array devices and peripheral devices.

Detailed ways

Embodiments of the invention will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. However, this invention may be embodied in various ways and should not be construed as limited to only the embodiments set forth herein. Like reference numerals refer to like elements throughout the specification.

It will be understood that, although the terms first, second etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element is referred to as being "on," "connected to," or "coupled to" another element, it can be directly on, connected to, or coupled to the other element, or it can also be directly on, connected to, or coupled to the other element. There is an inserted component. In contrast, when an element is referred to as being "directly on" or "directly connected to" or "directly coupled to" another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (eg, "between" versus "directly between," "adjacent" versus "directly adjacent "Wait). Here when an element is referred to as being on another element, it can be on or under the other element, directly coupled to the other element, or intervening elements may be present, or the elements may be separated by a gap or gap.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "the" and "the" are both intended to include the plural forms, unless the context clearly dictates otherwise. It should also be understood that the terms "comprises", "comprises", "includes" and/or "comprising", when used herein, designate the presence of stated features, integers, steps, operations, elements and/or components, But it does not exclude the existence or addition of one or more other features, integers, steps, operations, elements, components and/or combinations thereof.

As shown in FIG. 2 , it is a schematic device structure diagram according to a preferred embodiment of the present invention. A first silicon substrate 202 is included. In some embodiments, the first silicon substrate 202 may be made of single crystal silicon. In some embodiments, the first silicon substrate 202 may be made of other suitable materials, such as but not limited to, silicon germanium, germanium, silicon-on-insulator (SOI). Peripheral devices are formed on the first silicon substrate 202 . The peripheral devices include a plurality of transistors 206 . In some embodiments, an isolation region 204 and a doped region 208 are formed on the first silicon substrate 202 . The peripheral interconnection layer 222 covers the transistor 206 for electrical signal conduction. Interconnect layer 222 includes one or more contacts, such as contact 207 and contact 214 , and one or more interconnected conductor layers, such as layers 216 and 220 . Interconnect layer 222 further includes one or more interlayer insulating (ILD) layers, such as insulating layers 210 , 212 and 218 . The contacts are made of conductive materials including, but not limited to, tungsten, cobalt, copper, aluminum, and/or silicide. The conductive layer is made of conductive materials including, but not limited to, tungsten, cobalt, copper, aluminum, and/or silicide. The interlayer insulating layer is made of insulating materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, and/or doped silicon oxide.

Array devices are formed over the peripheral devices. The array device includes a plurality of NAND strings 230 extending through a plurality of conductor 234 and insulator 236 stacks 242 . Multiple conductor/insulator stacks 242 may also be referred to as a hierarchical layer stack. In some embodiments, hierarchical layer stack 242 may include more conductor layers or insulating layers made of different materials and/or different thicknesses than multiple conductor/insulator stacks. In some embodiments, conductor layer 234 is made of a conductive material including, but not limited to, tungsten, cobalt, copper, aluminum, doped silicon, and/or silicide. The insulating layer 236 is made of insulating materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride or a combination of the above materials. Multiple NAND strings 230 include semiconductor channels 228 and dielectric layer 229 . In some embodiments, semiconductor channel 228 is made of amorphous, polycrystalline, or monocrystalline silicon. In some embodiments, the dielectric layer 229 includes a tunnel layer, a memory cell layer and a barrier layer. The tunnel layer is made of silicon oxide, silicon nitride or a combination thereof. The barrier layer is made of silicon oxide, silicon nitride, high insulation constant insulating material or a combination thereof. The memory cell layer is made of silicon nitride, silicon oxynitride, silicon or a combination of the above materials.

In some embodiments, multiple NAND strings 230 include multiple control gates (or word lines). In some embodiments, conductor layer 234 acts as a control gate for the NAND strings. In some embodiments, the plurality of NAND strings 230 further includes select gates 238 formed near the upper ends of the NAND strings. In some embodiments, the plurality of NAND strings 230 further includes select gates 240 formed near the lower ends of the NAND strings. In some embodiments, select gates 238 and 240 are made of a conductive material including, but not limited to, tungsten, cobalt, copper, aluminum, doped silicon, and/or suicide.

In some embodiments, the plurality of NAND strings 230 further includes an epitaxial silicon layer 251 covering the upper ends of the semiconductor channels 228 formed in the NAND strings 230 . In some embodiments, epitaxial silicon layer 251 is formed from the epitaxial growth of single crystalline silicon layer 244 .

In some embodiments, the array device further includes one or more source contacts 232 extending through the hierarchical layer stack 242 . In some embodiments, source contact 232 is made of a conductive material including, but not limited to, tungsten, cobalt, copper, aluminum, and/or suicide.

In some embodiments, the array device further includes one or more word line contacts 258 . In some embodiments, a plurality of wordline contacts extend vertically within insulating layer 259 . In some embodiments, each of the plurality of wordline contacts has an end in contact with the wordline, whereby each wordline of the array device can be individually addressed by the wordline contacts. In some embodiments, each wordline contact is formed below and connected to the wordline. In some embodiments, the plurality of word line contacts are formed by wet etching or dry etching to form contact holes or contact trenches, and then filling the contact holes or contact trenches with a conductor (eg, tungsten). In some embodiments, filling the contact hole or contact trench includes depositing a barrier layer and/or an adhesion layer prior to depositing the conductor.

In some embodiments, the array device further includes a single crystal silicon layer 244 formed overlying the upper ends of the NAND strings 230 . In some embodiments, single crystal silicon layer 244 is made of single crystal silicon. In some embodiments, the monocrystalline silicon layer 244 may also be made of other materials, including but not limited to silicon germanium or germanium. In some embodiments, monocrystalline silicon layer 244 has doped regions 250 and isolation regions 246 .

In some embodiments, both the source contact 232 and the NAND string 230 are in contact with the single crystal silicon layer 244, so that when the single crystal silicon layer 244 conducts electrical signals, the source contact 232 can be electrically connected to the NAND string 230 ( For example, when the monocrystalline silicon layer 244 forms a conductive inversion layer).

In some embodiments, the array device further includes one or more through-array contacts 241 extending vertically through the hierarchical layer stack 242 . In some embodiments, the plurality of through-array contacts 241 transmit electrical signals from peripheral devices to back end of line (BEOL) layer 254 or pad layer 256 .

In some embodiments, the array interconnect layer 223 is formed over the peripheral interconnect layer 222 . In some embodiments, array interconnect layer 223 includes bitline contacts 226, wordline via contacts 257, one or more conductive layers (eg, layer 224), and one or more insulating layers (eg, insulating layer 225 and insulating layer 221). The conductor layer may be made of conductive materials including, but not limited to, tungsten, cobalt, copper, aluminum and/or silicide. The insulating layer is made of insulating materials, including but not limited to silicon oxide, silicon nitride, high insulating constant insulating materials or combinations thereof.

The bonding interface 219 is formed between the insulating layer 218 of the peripheral interconnection layer 222 and the insulating layer 221 of the array interconnection layer 223 . In some embodiments, bonding interface 219 may also be formed between conductor layer 224 and conductor layer 220 . In some embodiments, insulating layer 218 is a silicon nitride layer and insulating layer 221 is a silicon oxide layer. In some embodiments, insulating layer 218 is a silicon oxide layer and insulating layer 221 is a silicon nitride layer.

In some embodiments, the bit line contacts 226 contact the bottom ends of the plurality of NAND strings 230 . In some embodiments, each bitline contact 226 contacts a respective NAND string 230 such that the bitline contacts independently address each NAND string.

In some embodiments, the wordline via contact 257 is in contact with the lower end of the plurality of wordline contacts 258 . In some embodiments, each wordline via contact 257 is in contact with each wordline contact 258, whereby the wordline vias can be individually addressed for each NAND string.

The preferred embodiment shown in FIG. 2 further includes one or more back-end-of-line interconnect insulating and conductor layers (eg, conductor layer 248, conductor layer 254, and insulating layer 252) and liner layers (eg, liner layer 256). The back-end-of-line interconnect and liner layers carry electrical signals between the device of the embodiments and external circuitry. The back-end-of-line conductor layer may be made of conductive materials including, but not limited to, tungsten, cobalt, copper, aluminum, and/or silicide. The back-end-of-process insulating layer is made of insulating materials, including but not limited to silicon oxide, silicon nitride, high insulating constant insulating materials or combinations thereof. The liner layer is made of a conductive material including, but not limited to, tungsten, cobalt, copper, aluminum and/or silicide.

3A-3D are schematic diagrams of manufacturing steps of peripheral devices and peripheral interconnection layers of a NAND memory according to an embodiment of the present invention; FIG. 6 is a flowchart of an example method 600 of forming peripheral devices and peripheral interconnection layers.

The example method 600 begins at operation 602 , as shown in FIG. 6 , by forming peripheral devices on a first silicon substrate. As shown in FIG. 3A , firstly, a first silicon substrate 302 is provided to form peripheral devices. In some embodiments, the peripheral devices include a plurality of transistor devices 304 . The plurality of transistor devices 304 are formed on a first silicon substrate 302 . In some embodiments, forming transistor device 304 includes multiple steps, including but not limited to photolithography, dry/wet etching, thin film deposition, thermal growth, implantation, chemical mechanical planarization (CMP), and/or the above The combination. In some embodiments, a doped region 308 is also formed on the first silicon substrate 302 . In some embodiments, an isolation region 306 is also formed on the first silicon substrate 302 .

The example method 600 continues at operation 604 , as shown in FIG. 6 , by forming one or more insulating and conductive layers on the peripheral device. The one or more insulating layers and conductor layers are part of the peripheral interconnection layer, capable of transmitting electrical signals of peripheral devices. As shown in FIG. 3B , a first insulating layer 310 is formed on the first silicon substrate 302 , and a contact layer 308 is formed and electrically connected to peripheral devices. As shown in FIG. 3C , a second insulating layer 316 is formed on the first insulating layer 310 . In some embodiments, the second insulating layer 316 may be a combination of layers and formed in separate steps. The conductor layer 312 and the contact layer 314 are formed on the second insulating layer 316 . In some embodiments, conductor layer 312, contact layer 308, and conductor layer 314 are made of a conductive material. The process of forming the conductor layer and the contact layer may use a thin film deposition process, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) and electroplating process. The process of forming the conductor layer and the contact layer can also use photolithography, chemical mechanical planarization, dry/wet etching. The process of forming the insulating layer may use a thin film deposition process, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

The example method 600 continues at operation 606, as shown in FIG. 6, forming a top insulating layer and a top conductor layer of the peripheral interconnect layer. As shown in FIG. 3D , a third insulating layer 318 is formed on the second insulating layer 316 , and a conductive layer 320 is formed in the third insulating layer 318 . The peripheral interconnect layer 322 is thus formed. The process of forming the conductor layer may use a thin film deposition process, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) and electroplating process. The process of forming the conductor layer and the contact layer can also use photolithography, chemical mechanical planarization, dry/wet etching. The process of forming the insulating layer may use a thin film deposition process, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

4A-4D are schematic diagrams of manufacturing steps of an array device and an array interconnection layer of a NAND memory according to an embodiment of the present invention; FIG. 7 is a flow chart of an exemplary method 700 for forming an array device and an array interconnection layer.

The example method 700 begins at operation 702, as shown in FIG. 7, forming doped regions and isolation regions on a second silicon substrate. As shown in FIG. 4A, the second silicon substrate 402 is used to form an array device. In some embodiments, the doped region 404 is formed on the second silicon substrate 402 . In some embodiments, an isolation region 406 is formed on the second silicon substrate 402 . Forming the doped region 404 may use implantation and/or diffusion processes. The process of forming the isolation region 406 may adopt thermal growth or thin film deposition. Photolithography and dry/wet etching processes can be used to pattern the isolation regions.

The example method 700 continues with operation 704, as shown in FIG. 7, forming a plurality of insulating layer pairs on the second silicon substrate. As shown in FIG. 4B , a plurality of insulating layer pairs 410 and 412 are formed on the second silicon substrate 402 . In some embodiments, multiple insulating layer pairs form hierarchical layer stack 408 . In some embodiments, the pair of insulating layers includes a silicon nitride layer 410 and a silicon oxide layer 412 . In some embodiments, there are more pairs of insulating layers in the hierarchical layer stack 408 that are made of different materials and have different thicknesses. In some embodiments, the process of forming the plurality of insulating layer pairs may use a thin film deposition process, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

The example method 700 continues at operation 706 , as shown in FIG. 7 , forming a plurality of NAND strings of array devices on a second silicon substrate. As shown in FIG. 4C , a plurality of NAND strings 418 are formed on the second silicon substrate 402 . In some embodiments, insulating layer 410 in insulating layer pairs of hierarchical layer stack 408 may be replaced with conductive layer 416 , thereby forming multiple conductor/insulating layer pairs in hierarchical layer stack 414 . In some embodiments, the process of replacing the insulating layer 410 with the conductive layer 416 may use a wet etching method that is selective to the insulating layer 412 to etch the insulating layer 410, and this etching does not etch or slightly etches the insulating layer. 412 , and then fill the conductive layer 416 into the structure formed after the insulating layer 410 is etched. In some embodiments, CVD, ALD, and other suitable methods may be used to fill the conductive layer 416 . In some embodiments, conductor layer 416 is made of a conductive material including, but not limited to, tungsten, cobalt, copper, aluminum, and/or silicide. In some embodiments, forming a NAND string further includes forming a semiconductor channel 420 extending in a vertical direction through the hierarchical layer stack 414 . In some embodiments, forming the NAND string further includes a dielectric layer 422 positioned between the semiconductor channel 420 and the plurality of conductor/insulator layer pairs. In some embodiments, the dielectric layer 422 is a combination of multiple layers including, but not limited to, tunnel layers, memory cell layers, and barrier layers. In some embodiments, the tunnel layer includes an insulating material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or a combination of the above materials. In some embodiments, the memory cell layer includes materials that can be used to store charge to operate the NAND. The material of the memory cell layer includes but not limited to silicon nitride, silicon oxynitride, or a combination of silicon oxide and silicon nitride, or a combination of the above materials. In some embodiments, the barrier layer comprises an insulating material, such as a silicon oxide layer or a composite layer comprising silicon oxide/silicon nitride/silicon oxide (ONO). In some embodiments, the barrier layer may further include a high-K dielectric layer (eg, alumina). In some embodiments, ALD, CVD, PVD and other suitable methods may be used to form the dielectric layer 422 .

In some embodiments, forming the NAND string further includes forming an epitaxial layer at one end of the NAND string. Epitaxial layer 426 is formed at the bottom of NAND string 418 as shown in FIG. 4C . In some embodiments, epitaxial layer 426 is a silicon layer that is in direct contact with and epitaxially grown from second silicon substrate 402 . In some embodiments, epitaxial layer 426 is further doped to a desired doping level.

In some embodiments, operation 706 further includes forming one or more source contacts. As shown in FIG. 4C , a source contact 424 extending vertically through the hierarchical layer stack 414 is formed on the second silicon substrate 402 . In some embodiments, one end of the source contact 424 directly contacts the doped region 404 of the second silicon substrate 402 . In some embodiments, the source contact 424 is electrically connected to the plurality of NAND strings 418 through the contact doped region 404 of the second silicon substrate 402 . In some embodiments, select gate 428 is formed at the bottom of hierarchical layer stack 414 and controls conduction between source contact 424 and plurality of NAND strings 418 by switching contact doped region 404 of second silicon substrate 402 . In some embodiments, source contact 424 is made of a conductive material including, but not limited to, tungsten, cobalt, copper, aluminum, doped silicon, silicide, or combinations thereof. In some embodiments, the source contact 424 may be formed by using a dry/wet etching process to form an opening vertically penetrating through the hierarchical layer stack 414 , and then filling the opening with a conductive material or other material such as an insulating material. The filling material can use ALD, CVD, PVD and other suitable methods.

In some embodiments, operation 706 further includes forming one or more through-array contacts. As shown in FIG. 4C , through-array contacts 431 are formed on the second silicon substrate 402 . Through-array contacts 431 extend vertically and through hierarchical layer stack 414 . In some embodiments, one end of the through-array contact 431 enters the isolation region 406 of the second silicon substrate 402 . In some embodiments, the through-array contacts 431 may be formed by using a dry/wet etch process to form openings vertically through the hierarchical layer stack 414 and then filling the openings with conductive material. In some embodiments, other materials such as insulating material 433 partially fill the openings for isolation purposes. In some embodiments, through-array contacts 431 comprise conductive materials including, but not limited to, tungsten, cobalt, copper, aluminum, doped silicon, silicide, or combinations thereof. In some embodiments, ALD, CVD, PVD, and/or other suitable methods may be used to fill the openings with conductive or other materials.

In some embodiments, operation 706 further includes forming one or more word line contacts. As shown in FIG. 4C , word line contacts 425 are formed on the second silicon substrate 402 . The word line contact 425 extends vertically and penetrates the insulating layer 423 . In some embodiments, one end of the word line contact 425 is located on the word line of the NAND string. For example, one conductor layer 416 can serve as one word line of a NAND string. Thus, the word line contact 425 is electrically connected to the conductor layer 416 . In some embodiments, each of the wordline contacts 425 is connected to one conductor layer 416, whereby the conductor layer 416 is addressable through the wordline contacts. In some embodiments, word line contacts 425 can be further disposed on silicon substrate 402 or on a select gate of a NAND string (eg, select gate 428 and/or select gate 430 ). In some embodiments, forming the word line contact 425 includes forming a vertical opening through the insulating layer 423 using a dry/wet etch process, and then applying a conductor material or other material, such as for conductor filling, bonding and/or other The barrier layer material of interest fills the opening. In some embodiments, the conductor material that runs through the array contacts 425 is made of a conductor material including, but not limited to, tungsten, cobalt, copper, aluminum, doped silicon, silicide, or combinations thereof. In some embodiments, ALD, CVD, PVD, and/or other suitable methods may be used to fill the openings with conductive or other materials.

The example method 700 continues at operation 708 where, as shown in FIG. 7 , an array interconnect layer is formed on the plurality of NAND strings. As shown in FIG. 4D , an array interconnect layer 438 is formed over the plurality of NAND strings 418 . The array interconnect layer is used to transmit electrical signals between the NAND strings and other circuits. In some embodiments, forming array interconnect layer 438 includes forming insulating layer 434 and then forming a plurality of bit line contacts 432 in insulating layer 434 and in contact with NAND strings 418 . In some embodiments, the insulating layer 434 is one or more layers of insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. In some embodiments, the bit line contact 432 is formed by first forming an opening in the insulating layer 434 and then filling the opening with a conductive material or an insulating material. In some embodiments, the conductor material of the bit line contact 432 includes, but is not limited to, tungsten, cobalt, copper, aluminum, doped silicon, silicide, or a combination thereof. In some embodiments, ALD, CVD, PVD, and/or other suitable methods may be used to fill the openings with conductive or other materials.

In some embodiments, forming the array interconnect layer 438 further includes forming a plurality of word line via contacts 437 on the insulating layer 437 . In some embodiments, each wordline via contact 437 is in contact with one end of the wordline contact 425 to enable electrical connection. In some embodiments, the wordline via contact 437 is formed by forming an opening in the insulating layer 434 and then filling it with a conductive material. In some embodiments, prior to filling the conductive material, the opening is partially filled with other material, such as an insulating material, to enhance the viscosity or filling performance of the conductive material. In some embodiments, the conductive material forming the word line via contact includes, but is not limited to, tungsten, cobalt, copper, aluminum, doped silicon, silicide, or a combination thereof. In some embodiments, the opening is filled with a conductor material and an isolation material, and ALD, CVD, PVD, and/or other suitable methods may be used.

In some embodiments, forming the array interconnection layer 438 further includes forming other conductive layers, such as the conductor layer 440 and the conductor contact layer 444 in the insulating layer 434 . In some embodiments, there are one or more conductor layers 440 and/or conductor contact layers 444 . In some embodiments, the conductive material for making the conductive layer 440 and the conductive contact layer 444 includes, but is not limited to, tungsten, cobalt, copper, aluminum, doped silicon, silicide, or a combination thereof. The process of forming the conductor layer and the conductor contact layer can adopt a known back-end process method.

In some embodiments, forming the array interconnection layer 438 further includes forming a top conductive layer 442 and a top insulating layer 436 . In some embodiments, the conductive material for making the top conductive layer 442 includes, but is not limited to, tungsten, cobalt, copper, aluminum, doped silicon, silicide, or a combination thereof. In some embodiments, the insulating material for making the top insulating layer 436 includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, or a combination of the above materials.

5A-5C are schematic diagrams of steps of combining the aforementioned array device and peripheral devices according to an embodiment of the present invention; FIG. 8 is a flowchart of an example method 800 of combining the aforementioned array device and peripheral devices.

Exemplary method 800 starts at step 802. As shown in FIG. 8, the array device on the second silicon substrate is turned upside down so that the array interconnection layer is located under the second silicon substrate, and the array interconnection layer and the peripheral interconnection layer are aligned. As shown in FIG. 5A , an array interconnection layer 438 is disposed under the second silicon substrate 402 . In some embodiments, the method of aligning the array interconnection layer 438 and the peripheral interconnection layer 322 is to align the conductor layer 442 of the array interconnection layer 438 and the conductor layer 320 of the peripheral interconnection layer 322 . As such, the conductor layer 442 is in contact with the 320 when the array device and the peripheral device are combined.

Exemplary method 800 continues at step 804, as shown in FIG. 8, in conjunction with the array interconnect layer and the peripheral interconnect layer. As shown in FIG. 5B , the array interconnection layer 438 and the peripheral interconnection layer 322 are combined to form an adhesive interface 503 . In some embodiments, as shown in FIG. 5A , before or when the two interconnect layers are bonded, the treatment process 502 can be used to strengthen the bonding force between the array interconnect layer and the peripheral interconnect layer. In some embodiments, insulating layer 436 is a silicon oxide layer and insulating layer 318 is a silicon nitride layer. In some embodiments, insulating layer 436 is a silicon nitride layer and insulating layer 318 is a silicon oxide layer. In some embodiments, the treatment process 502 includes a plasma treatment process to treat the surface of the array interconnect layer and the surface of the peripheral interconnect layer to enhance the chemical bond formed between the two insulating layers 436 and 318 . In some embodiments, the treatment process 502 includes a wet chemical treatment process that treats the surface of the array interconnect layer and the surface of the peripheral interconnect layer to enhance the chemical bond formed between the two insulating layers 436 and 318 .

In some embodiments, the treatment process 502 is a heat treatment process performed in a bonding process. In some embodiments, the operating temperature of the heat treatment is 250°C to 600°C. In some embodiments, the heat treatment process causes interdiffusion between the conductor layers 442 and 320 . Thus, the conductors 442 and 320 are mixed with each other after the bonding process. In some embodiments, both conductor layers 442 and 320 are made of copper.

Exemplary method 800 continues at step 806, as shown in FIG. 8, by thinning the second silicon substrate to form a monocrystalline silicon layer. As shown in FIG. 5B , according to an embodiment of the present invention, the second silicon substrate 402 is thinned to form a single crystal silicon layer 504 . In some embodiments, the thickness of the monocrystalline silicon layer 504 is between 200 nm and 5000 nm after thinning. In some embodiments, the thickness of the monocrystalline silicon layer 504 is between 150 nm and 50 μm. In some embodiments, the process of thinning the second silicon substrate 402 includes but not limited to wafer grinding, dry etching, wet etching, chemical mechanical polishing or a combination of the above processes.

Exemplary method 800 continues at step 808 , as shown in FIG. 8 , by forming a back-end-of-line interconnection layer and a liner layer on the single crystal silicon layer. As shown in FIG. 5C , a back-end-of-process interconnection layer and a liner layer 512 are formed on the single crystal silicon layer 504 . In some embodiments, the back-end-of-line interconnect layer includes one or more insulating layers 506 , one or more contacts 508 , and one or more conductor layers 510 . In some embodiments, insulating layer 506 is a combination of multiple insulating layers, which may be fabricated in separate steps. In some embodiments, contacts 508, conductor layer 510, and liner layer 512 may be made of conductive materials including, but not limited to, tungsten, cobalt, copper, aluminum, doped silicon, silicide, or combinations thereof. In some embodiments, the insulating material for making the insulating layer 506 includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, or a combination of the above materials. In some embodiments, insulating layer 506 may further include a high-K insulating material. In some embodiments, pad layer 512 is connected to external circuitry to pass electrical signals between the combined array/peripheral device and the external circuitry.

In a word, the present invention separates the manufacture of the array device and the peripheral device, avoiding the manufacturing process of the two devices affecting each other during manufacture, and solving the problem in the prior art that the manufacture of the latter layer is limited by the temperature after the manufacture of the front layer , obtained high device density and good peripheral device performance.

The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present invention can easily think of changes or Replacement should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (11)

1. A NAND memory, comprising: Silicon substrate; one or more peripheral devices; one or more NAND strings formed over the peripheral device; a monocrystalline silicon layer formed over the one or more NAND strings, the monocrystalline silicon layer being in contact with the one or more NAND strings, and One or more first interconnect layers are formed between the one or more peripheral devices and the one or more NAND strings. 2. A kind of NAND memory as claimed in claim 1, wherein, each NAND string comprises: multiple conductor/insulator stacks; semiconductor vias extending vertically through the plurality of conductor/insulator stacks; forming a tunnel layer between the plurality of conductor/insulator stacks and the semiconductor channel; and a memory cell layer formed between the tunnel layer and a plurality of conductor/insulator stacks. 3. A NAND memory as claimed in claim 1, further comprising one or more first contacts, wherein each of said first contacts extends vertically and has a connection with said plurality of conductors of said NAND string The upper end of the conductor layer of the insulator stack is contacted, and wherein each first contact is formed on the lower end of said conductor layer and is contact-connected with the conductor layer. 4. A kind of NAND memory as claimed in claim 1, further comprising one or more second contacts, wherein said second contacts vertically pass through said plurality of conductor/insulator stacks, and said first The upper ends of the two contacts are in contact with the single crystal silicon layer. 5. A NAND memory according to claim 1, further comprising a second interconnection layer formed above the plurality of NAND strings, wherein the second interconnection layer includes one or more interconnections formed on one or more A conductor layer within an insulating layer. 6. A NAND memory as claimed in claim 1, wherein said plurality of NAND strings comprises one NAND string formed on another NAND string. 7. A kind of NAND memory as claimed in claim 6, wherein, said NAND string formed on another NAND string communicates with another NAND string through a conductor portion formed between said NAND string and another NAND string NAND string connection. 8. A method of manufacturing a NAND memory, comprising: forming one or more peripheral devices on the first silicon substrate; forming one or more NAND strings on a second silicon substrate; placing the one or more NAND strings over the one or more peripheral devices such that a second silicon substrate is over the one or more NAND strings; bonding the one or more NAND strings and the one or more peripheral devices together through a bonding process; and The second silicon substrate is thinned to form a single crystal silicon layer over the one or more NAND strings. 9. The method of claim 8, wherein forming the NAND string comprises forming a plurality of conductor/insulator stacks on the second silicon substrate. 10. The method of claim 8, further comprising forming one or more first contacts, wherein each of said first contacts extends vertically and has a connection with said plurality of conductors/ The contact terminal of the conductor layer of the insulator stack. 11. The method of claim 8, further comprising forming a first interconnect layer of the one or more NAND strings over the second silicon substrate to connect the NAND strings to the one or more peripheral devices.