Dremo

The ubiquity of threshold voltage relaxation is demonstrated in samples with both conventional and high-k dielectrics following various stress conditions. A technique based on recording short traces of relaxation during each measurement phase of a standard measure-stress-measure sequence allows monitoring and correcting for the otherwise-unknown relaxation component. The properties of relaxation are discussed in detail for pFET with SiON dielectric subjected to NBTI stress. Based on similarities with dielectric relaxation, a physical picture and an equivalent circuit are proposed.

The large FET devices of the past were considered identical in terms of electrical performance. Consequently, the same workload resulted in an identical parameter shift in all devices. As downscaling of FET devices progressed, the gate dielectric was the first to reach nanometer dimensions, thus introducing the first stochastically distributed reliability mechanism-time dependent dielectric breakdown [1]. With the downscaling of lateral device dimensions to atomic levels, variation among devices appeared due to effects such as random dopant fluctuation [2-4] and line edge roughness [5]. Similarly, application of the identical workload in such devices results in distributions of the parameter shifts [6].

Positive charge trapped in the SiO͑N͒ gate dielectric of deeply-scaled p-channel metal-oxide-semiconductor field-effect transistors is observed after both negative and positive gate bias temperature stress. Emission of elementary trapped charges is demonstrated and analyzed through the quantized threshold voltage transients observed after stress. The magnitude distribution of the threshold voltage steps is used to estimate the depth of the traps in the gate dielectric to be about 0.5 nm from the injecting silicon-dielectric interface in both cases.

The energy and spatial profiling of the interface and near-interface traps in n-channel MOSFETs with SiO 2 /Al 2 O 3 gate dielectrics is investigated by charge-pumping (CP) measurements. By increasing the amplitude as well as lowering the frequency of the gate pulse, an increase of the charge recombined per cycle was observed, and it was explained by the contributions of additional traps located higher in energy and deeper in position at the SiO 2 /Al 2 O 3 interface. In addition, CP currents, acquired after different constant voltage stress, have been used to investigate the trap generation in this dielectric stack.

Extraction of interfacial trap density N it in extremely reduced gate oxides with equivalent oxide thickness (EOT) below 1 nm by conventional charge pumping is virtually impossible due to the high gate leakage current through the very thin oxide. However, interface quality assessment in subnano EOT devices is essential for the reliability and performance improvement of future logic devices. In this paper, an accurate approach to determine the interfacial trap density in a 5.8-Å EOT device is performed by an advanced charge pumping technique employing ring-oscillator-connected devices. A consistency comparison of this technique to the conventional charge pumping is done by a frequency sweep on the 10.1-Å EOT device. Clear charge pumping currents are obtained on the 5.8-Å EOT oxide, and further analysis by varying the applied frequency and amplitude is performed. The interface trap density in the 5.8-Å EOT device is found to be higher than that in the 10.1-Å EOT device due to the physically reduced interfacial layer in the thinner EOT device. Moreover, direct tunneling-based calculation gives the charge injection distance as about 2 Å inside the oxide. Stress-induced defect generation is investigated by applying dc stress between charge pumping and I drain −V gate measurements. The 5.8-Å EOT device shows higher initial N it but lower stress-induced N it as compared with the 10.1-Å EOT device. The bulk trap N ot generated after stress is higher in the 5.8-Å EOT device due to the higher initial bulk trap density.

The influence of FET gate oxide breakdown on the performance of a ring oscillator circuit is studied using statistical tools, emission microscopy, and circuit analysis. It is demonstrated that many hard breakdowns can occur in this circuit without affecting its overall function. Time-to-breakdown data measured on individual FETs are shown to scale correctly to circuit level. SPICE simulations of the ring oscillator with the affected FET represented by an equivalent circuit confirm the measured influence of the breakdown on the circuit's frequency, the stand-by and the operating currents. It is concluded that if maintaining a digital circuit's logical functionality is the sufficient reliability criterion, a nonzero probability exists that the circuit will remain functional beyond the first gate oxide breakdown. Consequently, relaxation of the present reliability criterion in certain cases might be possible.

We report extensive experimental results of the negative bias temperature instability (NBTI) reliability of SiGe channel pMOSFETs as a function of the main gate-stack parameters. The results clearly show that this high-mobility channel technology offers significantly improved NBTI robustness compared with Si-channel devices, which can solve the reliability issue for sub-1-nm equivalent-oxide-thickness devices. A physical model is proposed to explain the intrinsically superior NBTI robustness.

In this paper it is demonstrated in a wide stress field range that breakdown in thin oxide layers occurs as soon as a critical density of neutral electron traps in the oxide is reached. It is proven that this corresponds to a critical hole fluence, since a unique relationship between electron trap generation and hole fluence is found independent of stress field and oxide thickness. In this way literature models relating breakdown to hole fluence or to trap generation are linked. A new model for intrinsic breakdown, based on a percolation concept, is proposed. It is shown that this model can explain the experimentally observed statistical features of the breakdown distribution, such as the increasing spread of the QBD-distribution for ultrathin oxides.

We present an experimental methodology that demonstrates the suitability of the conventional three-lumpedparameter model for gate impedance of MOSFET devices at frequencies from dc to the gigahertz range, which permits accurate extraction of model parameters. The parasitic effects at a high frequency are minimized by using radio frequency techniques (i.e., short return paths and de-embedding structures), whereas a robust parameter extraction algorithm overcomes possible instrument inaccuracies. When combined, these allow simultaneous extraction of all three parameters (i.e., C gate , R DT , and R series ) from the model. The technique is applied to conventional SiO 2 -based MOSFET devices and to ultraleaky HfO 2 devices with aggressively scaled gate dielectric thickness.

In this paper, we study time-dependent dielectric breakdown in thin gate oxides and propose a new methodology applicable to a wide range of gate stacks for extracting soft breakdown (SBD) and post-SBD wear-out (WO) parameters from measuring the time to hard breakdown (t HBD ) only. By introducing this methodology, we can get around the problems related to the detection of the first SBD and the corresponding WO time. We show that the shape of the HBD distribution can change with voltage and area, depending on the ratio of WO and SBD times. We also explain why, in literature, contradictory results related to the voltage acceleration factors of SBD and WO are reported. Finally, we construct a complete reliability prediction model that includes SBD and WO.

The parasitic bipolar transistor inherent to grounded gate nMOS transistors is modelled, accounting for the specific conditions applied by CDM ESD stress. The avalanching of both, drain and source, the triggering of snapback and the CDM-specific bipolar saturation mode are addressed. Furthermore, a fast analytical method to determine CDM ESD lumped tester parasitics from measured pulse characteristics is presented. The triggering of the grounded gate nMOS transistor under CDM is studied in detail for different gate lengths. The optimal gate length for CDM protection in advanced submicron technologies is discussed.

Several trends occurring in the past few years in our understanding of bias temperature instability ͑BTI͒ are reviewed. Among the most important is the shift toward analyzing BTI relaxation with the tools originally developed for describing low-frequency noise. This includes the interpretation of the time, temperature, voltage, and duty cycle dependences. It is shown that a wealth of information about gate oxide defect properties can be obtained from deeply scaled devices and correctly modeled based on nonradiative multiphonon theory. It is then shown how detailed understanding of individual defect properties can allow interpreting the variability issues of future complementary metal-oxide semiconductor technologies. This is complemented by showing the most promising technological solutions for BTI.

The impact of V th -adjusting layers on high-k/metal-gate n-and pFinFET V th stability is investigated. Additional insight is gained by monitoring ⌬V th recovery transients over several decades in time. V th -adjusting capping layers deposited directly on top of the gate dielectric degrade the V th stability. The V th stability improves as the capping layers are buried in the gate metal and are thus isolated from the gate dielectric. A combination of a capping layer thickness and depth in the metal gate is found that practically eliminates nFET V th instability.

State-of-the-art germanium-based p-channel FET devices are shown to have normal Negative Bias Temperature Instability (NBTI) behavior typically observed in Silicon-based pFETs. Furthermore, NBTI in Ge pFETs is reduced with respect to their Si counterparts. This improvement quantitatively corresponds to the reduction due to the tunneling barrier for holes formed by the Si passivation layer. A strong reduction in the permanent NBTI component is ascribed to a higher initial number of interface states.

The negative bias temperature instability (NBTI) of nanoscaled Si 0.45 Ge 0.55 pFETs with different thicknesses of the Si passivation layer (cap) is studied. Individual discharge events are detected in the measured threshold voltage shift (DV th ) relaxation traces, with exponentially distributed step heights. The use of a thinner Si cap is shown to reduce both the average number of charge/discharge events and the average DV th step height. To qualitatively explain the experimental observations, a simple model including a defect band in the dielectric is proposed.

In this paper we demonstrate superior NBTI reliability of SiGe pFETs with ultra-thin EOT in a Replacement Metal Gate (RMG) process flow, and in a SiGe channel bulk pFinFET architecture. Moreover, we investigate the Forward Body Bias (FBB) technique showing that it can very efficiently improve the SiGe device I ON without compromising the NBTI reliability, or vice versa further improve the device reliability without compromising the I ON . Based on the insights provided by the Body Bias experiments, we propose a model for the superior SiGe NBTI reliability which can explain all the experimental observations.

By scanning 1/3 nm SiO 2 /HfSiO(N) gate dielectrics with variable t charge Àt discharge amplitude charge pumping technique (VT 2 ACP) and slow rate I d V g hysteresis, we study in detail the energy profile and estimate the spatial position (within SiO 2 or HKs layer) of pre-stress and stress-induced electron traps. Pre-stress traps are mainly at shallow energy levels while stress-induced traps are at deeper energy levels. We demonstrate that due to incomplete discharge of bulk traps, the commonly-used base level charge pumping (CP) sweep is not suited for trap energy profiling. Further, we show that in CP measurements, due to the non-negligible tail of the filling probability of traps, even at short charge times, a fraction of HK-bulk traps is scanned in addition to interfacial traps. When the trap density in the HK is significantly higher than in the IL, this fraction might dominate the CP signal and can cause misinterpretation of data. Finally, we point out the possible contribution of the initially-present traps in the formation of a percolation path causing the dielectric breakdown.

This paper presents the general and analytical solution of a fourth-order lumped element model (LEM) to describe human body model (HBM) electrostatic discharge (ESD) testers including the main tester parasitic elements. The analytical fitting to the LEM of experimentally obtained HBM pulse data is a new scientifically justified tool to determine HBM tester parasitic elements. The impact of the test board capacitance on HBM testing is demonstrated and explained. Furthermore, the MIL 883C/3015.71 and EOS/ESD S5.1-19912 Standards on HBM testers are evaluated upon their selectivity to the test board capacitance. Finally, recommendations to improve HBM tester specifications regarding their selectivity to the parasitic test board capacitance are formulated KEY WORDS ESD HBM testing Parasitics extraction MIL 883C/3015.7 EOS/ESD S5.1-1991 a 350 MHz minimum bandwidth oscilloscope, On (product 1). On each tester 64 data points were taken

Local oxide capacitance as a crucial parameter for characterization of hot-carrier degradation in long-channel n-MOSFETs J. Vac. Sci. Technol. B 31, 01A118 (2013) Mitigation of extreme ultraviolet mask defects by pattern shifting: Method and statistics J. Vac. Sci. Technol. B 30, 051605 (2012) Gallium nitride nanowire electromechanical resonators with piezoresistive readout J. Vac. Sci. Technol. B 29, 052001 (2011)

We consider in detail the aspects of maximizing application performance while maintaining its sufficient reliability on the specific case of serially connected nFETs. Serially connected nFETs used in some digital CMOS applications, such as SRAM decoder circuits, and dynamic logic, are vulnerable to Positive Bias Temperature Instability (PBTI). Here we discuss the impact of PBTI frequency and workload on high-k/metal gate nFETs in terms of Capture and Emission Time (CET) maps and quantitatively explain the degradation of our test circuit. This constitutes one of the first validations of the CET map-based methodology on a real silicon circuit. From individual trapping events in deeply scaled nFETs we then project PBTI distributions at 10 years. We further show that at increased supply voltage the serially connected nFET speed degradation is outweighed by signal transfer speedup, resulting in a net performance improvement. Finally, we discuss other degradation mechanisms and conclude the reliability in the studied case will be limited by hard gate oxide breakdown.