Electrical and Computer Engineering and Informatics

Genetic Algorithm (GA) is a directed random search technique working on a population of solutions and based on natural selection. However, its convergence to the optimum may be very slow for complex optimization problems, especially when the GA is software implemented, making it difficult to be used in real time applications. In this paper a parameterized GA Intellectual Property (IP) core is designed and implemented on hardware, achieving impressive time-speedups when compared to its software version. The parameterization stands for the number of population individuals and their bit resolution, the bit resolution of each individual's fitness, the number of elite genes in each generation, the crossover and mutation methods, the maximum number of generations, the mutation probability and its bit resolution. The proposed architecture is implemented in a Field Programmable Gate Array Chip (FPGA) with the use of a Very-High-Speed Integrated Circuits Hardware Description Language (VHDL) and advanced synthesis and place and route tools. The GA discussed in this work achieves a frequency rate of 92 MHz and is evaluated using the Traveling Salesman Problem (TSP) as well as several benchmarking functions.

This paper describes an improved approach to design a Takagi-Sugeno zero-order type fast parameterized digital fuzzy logic controller (DFLC) processing only the active rules (rules that give a non-null contribution for a given input data set), at high frequency of operation, without significant increase in hardware complexity. To achieve this goal, an improved method of designing the fuzzy controller model is proposed that significantly reduces the time required to process the active rules and effectively increases the input data processing rate. The DFLC discussed in this paper achieves an internal core processing speed of at least 200 MHz, featuring two 8-bit inputs and one 12-bit output, with up to seven trapezoidal shape membership functions per input and a rule base of up to 49 rules. The proposed architecture was implemented in a field programmable gate array (FPGA) chip with the use of a very high-speed integrated-circuits hardware-description-language (VHDL) and advanced synthesis and place and route tools

In this paper a System-on-a-Chip (SoC) for the path following task of autonomous non-holonomic mobile robots is presented. The SoC consists of a digital fuzzy logic processor and a flow control program that runs under the Xilinx Microblaze™ soft processor core. The fuzzy processor implements a fuzzy path tracking algorithm introduced by the authors. The system was tied to an actual P3-DX8 robot and field experiments have been performed in order to assess the overall performance. Quantization problems and limitations imposed by the system configuration are also discussed.

Background Autonomous control of surgical robotic platforms may offer enhancements such as higher precision, intelligent manoeuvres, tissuedamage avoidance, etc. Autonomous robotic systems in surgery are largely at the experimental level. However, they have also reached clinical application.

This paper focuses on the Field Programmable Gate Array (FPGA) design and implementation of intelligent control system applications on a chip, specifically fuzzy logic and genetic algorithm processing units. Initially, an overview of the FPGA technology is presented, followed by design methodologies, development tools and the use of hardware description languages (HDL). Two FPGA design examples with the use of Hardware Description Languages (HDLs) of parameterized fuzzy logic controller cores are discussed. Thereinafter, a System-on-a-Chip (SoC) designed by the authors in previous work and realized on FPGA featuring a Digital Fuzzy Logic Controller (DFLC) and a soft processor core for the path tracking problem of mobile robots is discussed. Finally a Genetic Algorithm implementation (previously published by the authors) in FPGA chip for the Traveling Salesman Problem (TSP) is also discussed.

Ένα από τα πιο σοβαρά μειονεκτήματα των ευφυών αλγορίθμων ελέγχου που έχουν αναπτυχθεί σε λογισμικό, είναι κυρίως ο χρόνος εκτέλεσής τους και η αυξημένη ανάγκη υπολογιστικών πόρων. Για παράδειγμα, στην περίπτωση των γενετικών αλγορίθμων η σύγκλισή τους προς το βέλτιστο μπορεί να είναι υπερβολικά αργή για δύσκολα και περίπλοκα προβλήματα βελτιστοποίησης, με αποτέλεσμα να είναι αδύνατη η χρήση τους σε εφαρμογές πραγματικού χρόνου. Έτσι γίνεται άμεσα αντιληπτό ότι η εφαρμογή των αλγορίθμων αυτών σε ρομποτικές εφαρμογές πραγματικού χρόνου (real-time) καθιστά τις υλοποιήσεις σε λογισμικό ανεπαρκείς. Βάση του τελευταίου, τα τελευταία χρόνια λόγω της ταχείας ανάπτυξης στην τεχνολογία των ψηφιακών κυκλωμάτων, έχει αναφερθεί ένας σημαντικά μεγάλος αριθμός ερευνητικών εργασιών που ασχολούνται με υλοποιήσεις ευφυών αλγορίθμων σε υλικό.

The paper describes a low computational power method for detecting sensor faults. A typical fault detection unit for multiple sensor fault detection with modelbased approaches, requires a bank of estimators. The estimators can be either observer or artificial intelligence based. The proposed control scheme uses an artificial intelligence approach for the development of the fault detection unit abbreviated as 'i-FD'. In contrast with the bank-estimators approach the proposed i-FD unit is using only one estimator for multiple sensor fault detection. The efficacy of the scheme is tested on an Electro-Magnetic Suspension (EMS) system and compared with a bank of Kalman estimators in simulation environment.