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Fig. 4. Equivalent circuits for operation modes of the proposed DC-DC convrter. (a) Mode I; (b) Mode II; (c) Mode III; (d) Mode IV. Applying the KVL to the loops is Fig. 4, in modes // ai IV, the voltage across Lm is determined as:

Figure 4 Equivalent circuits for operation modes of the proposed DC-DC convrter. (a) Mode I; (b) Mode II; (c) Mode III; (d) Mode IV. Applying the KVL to the loops is Fig. 4, in modes // ai IV, the voltage across Lm is determined as:

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Fig. 1. General structure of solar PV-based renewable energy system. high voltage stress across the semiconductor devices, reverse- recovery problem of the output diode, high electromagnetic interference (EMI), and effective series resistance (ESR) of the passive elements leading to low efficiency [4-6].
Fig. 1. General structure of solar PV-based renewable energy system. high voltage stress across the semiconductor devices, reverse- recovery problem of the output diode, high electromagnetic interference (EMI), and effective series resistance (ESR) of the passive elements leading to low efficiency [4-6].
Fig. 2. (a) Structure of the proposed converter; (b) Equivalent circuit of the proposed converter.
Fig. 2. (a) Structure of the proposed converter; (b) Equivalent circuit of the proposed converter.
To simplify the steady-state analysis, the leakage inductances are ignored and the CI is assumed to be well coupled. Neglecting the leakage inductances, operation modes I and J/I are ignored, and then the operation principle is simplified to two main modes // and JV. In mode //, switches S; and S2 turn on and the magnetizing inductance Lm is charged, however Lm is discharged in mode JV when S; and S> turn off. N=N>2/N; is the turns-ratio of the CI, and the duty cycle range of the proposed converter is from 0 to 0.5. Fig.3. The gate signals and time intervals of operation modes for the proposed converter.
To simplify the steady-state analysis, the leakage inductances are ignored and the CI is assumed to be well coupled. Neglecting the leakage inductances, operation modes I and J/I are ignored, and then the operation principle is simplified to two main modes // and JV. In mode //, switches S; and S2 turn on and the magnetizing inductance Lm is charged, however Lm is discharged in mode JV when S; and S> turn off. N=N>2/N; is the turns-ratio of the CI, and the duty cycle range of the proposed converter is from 0 to 0.5. Fig.3. The gate signals and time intervals of operation modes for the proposed converter.
Fig. 5. Static voltage gain of the proposed converter as the function of duty cyle and turns-ratio.
Fig. 5. Static voltage gain of the proposed converter as the function of duty cyle and turns-ratio.
From (10) and (11), it is clear that the voltage stresses on the power devices are less than the output voltage, which enables the designer to select low-voltage-rated switches and diodes with low ON-state resistance, which causes lower switching and conduction losses. Additionally, it can be seen that as the turns-ratio of CI increases, the voltage stresses of the power switches decrease with respect to the output voltage.
From (10) and (11), it is clear that the voltage stresses on the power devices are less than the output voltage, which enables the designer to select low-voltage-rated switches and diodes with low ON-state resistance, which causes lower switching and conduction losses. Additionally, it can be seen that as the turns-ratio of CI increases, the voltage stresses of the power switches decrease with respect to the output voltage.
According to the ampere-second balance law, the average current of the capacitors is zero for a switching cycle. Knowing this fact, the average current relationships of inductors and semiconductor devices can be derived as: A comparison between the proposed converter and other similar topologies in [19] and [20] in terms of the voltage gain, normalized voltage stresses on the semiconductor devices, and the number of elements is presented in Table /. According to Table J, the proposed converter and the ones in [19] and [20] have the same number of components (i.e., 12) and the same duty cycle range from 0 to 0.5. Voltage gains of the converters are also plotted in Fig. 6 for N=2. As observed, the proposed converter has higher voltage gain than converters introduced in [19] and [20]. Fig. 7 illustrated the normalized voltage stress across the power switches versus the turns-ratio. It can be seen that as the turns-ratio increases, the normalized voltage stress on the switch decreases and is always less than 1 for all three converters. The maximum normalized voltage stress on the diodes versus the turns-ratio is shown in Fig. 8, which is equal to 1 for the converter in [19] but less than 1 for the proposed converter and the converter in [20]. As a result, the voltage stresses on the power switches and diodes of the proposed converter are less than the output voltage, which leads to the
According to the ampere-second balance law, the average current of the capacitors is zero for a switching cycle. Knowing this fact, the average current relationships of inductors and semiconductor devices can be derived as: A comparison between the proposed converter and other similar topologies in [19] and [20] in terms of the voltage gain, normalized voltage stresses on the semiconductor devices, and the number of elements is presented in Table /. According to Table J, the proposed converter and the ones in [19] and [20] have the same number of components (i.e., 12) and the same duty cycle range from 0 to 0.5. Voltage gains of the converters are also plotted in Fig. 6 for N=2. As observed, the proposed converter has higher voltage gain than converters introduced in [19] and [20]. Fig. 7 illustrated the normalized voltage stress across the power switches versus the turns-ratio. It can be seen that as the turns-ratio increases, the normalized voltage stress on the switch decreases and is always less than 1 for all three converters. The maximum normalized voltage stress on the diodes versus the turns-ratio is shown in Fig. 8, which is equal to 1 for the converter in [19] but less than 1 for the proposed converter and the converter in [20]. As a result, the voltage stresses on the power switches and diodes of the proposed converter are less than the output voltage, which leads to the
Fig. 6. Voltage gain versus duty cycle for N=2. PERFORMANCE COMPARISON BETWEEN THE PROPOSED CONVERTER AND OTHER STEP-UP DC-DC CONVERTERS
Fig. 6. Voltage gain versus duty cycle for N=2. PERFORMANCE COMPARISON BETWEEN THE PROPOSED CONVERTER AND OTHER STEP-UP DC-DC CONVERTERS
Fig. 8. Maximum normalized voltage stress on diodes versus turns-ratio.
Fig. 8. Maximum normalized voltage stress on diodes versus turns-ratio.
“ig. 7. Normalized voltage stress on switch versus turns-ratio.
“ig. 7. Normalized voltage stress on switch versus turns-ratio.
ABLE II. CONVERTER OPERATION PARAMETERS Co, and C3 are 80 V, 80 V, 120 V, and 400 V, respectively. These calculated capacitors voltages are equal to the simulation values shown in Fig. 9. There is a little difference between the calculated and simulated voltage values, which is led by the leakage inductances of the CI and parasitic elements of the semiconductors devices modeled in the simulation. The calculated voltage stresses on semiconductor devices are Vs =V99=Vp1=Vp2=V pa=80 V and Vp3=V po= 320 Vv matching with the simulation results illustrated in Fig. 10. Fig. 11 shows the simulated current waveforms of the magnetizing inductance, leakage inductances, and input current. According to the simulated current itm, which is continuous and nonzero, the proposed converter operates in CCM. The observed average value is approximately 10 A for currents ijn and itm and 0 A for current itx2, which is in agreement with the calculated value from (12) and (13). According to Fig. 11, all the currents increase during the ON-state of the switching S; and S2(modes I and JI), while decrease during OFF-state of switches (modes II and IV).
ABLE II. CONVERTER OPERATION PARAMETERS Co, and C3 are 80 V, 80 V, 120 V, and 400 V, respectively. These calculated capacitors voltages are equal to the simulation values shown in Fig. 9. There is a little difference between the calculated and simulated voltage values, which is led by the leakage inductances of the CI and parasitic elements of the semiconductors devices modeled in the simulation. The calculated voltage stresses on semiconductor devices are Vs =V99=Vp1=Vp2=V pa=80 V and Vp3=V po= 320 Vv matching with the simulation results illustrated in Fig. 10. Fig. 11 shows the simulated current waveforms of the magnetizing inductance, leakage inductances, and input current. According to the simulated current itm, which is continuous and nonzero, the proposed converter operates in CCM. The observed average value is approximately 10 A for currents ijn and itm and 0 A for current itx2, which is in agreement with the calculated value from (12) and (13). According to Fig. 11, all the currents increase during the ON-state of the switching S; and S2(modes I and JI), while decrease during OFF-state of switches (modes II and IV).
Fig. 10. Simulated waveforms of semiconductors voltages. Fig. 9. Simulated waveforms of capacitors voltages.
Fig. 10. Simulated waveforms of semiconductors voltages. Fig. 9. Simulated waveforms of capacitors voltages.
Fig. 11. Simulated waveforms of currents itm, iLk1, ixk2, aNd lin.
Fig. 11. Simulated waveforms of currents itm, iLk1, ixk2, aNd lin.
Related topics:
PhotovoltaicsRenewable energy resourcesPower Electronics ConverterHigh step up converter
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