Fig. 2. MPEG2 profiling (fast ME). Coprocessor ISA Fig. 4. Vectorized MPEG2 TMS instruction count reduction (FSME). Fig. 6. High-level view of system. Fig. 5. Vectorized FSME and fast ME performance relative to scalar FSME (Set 1). Fig. 7. Processor/coprocessor microarchitecture. Fig. 9. Vector register file (dual-port SRAM based). Fig. 10. Latch-based register file pipeline. Fig. 12. Scalar registers and update logic. VLSU performance (clocks/per/operation) Table 2 support for the vector datapath however, does not include un-aligned vector load/store operations as is the case with the RTL (Leon-2) model. A further point contributing to the better performance of the C-based simulation is the non-blocking Load/Store unit which, in the case of the Leon-2 model, uses a blocking configuration (sub-block misses during un-aligned vector accesses are a major source of stall cycles as two sub-blocks are fetched from memory). This is further exaggerated by the coherency logic of the VLSU which has extended the latency of a refill request appearing on the AHB. Finally, though the Simplescalar model was configured for single-issue/in-order operation it still models a more aggressive pipeline than the standard Leon-2 5-stage pipeline. ia. a Fig. 13. Algorithm execution-time Data Cache study. Fig. 14. Vector data Cache configuration. Fig. 15. High-speed local memory configuration. Fig. 16. Coprocessor control pipeline schematic. To seamlessly integrate the coprocessor ISA to the existing Sparc V8 ISA, the unimp opcode was redefined as our study found that it is not produced by our Spare compiler. The decoding logic of the scalar CPU was modified such as not to generate an invalid instruction exception when the hijacked opcode was encountered. In addition, a number of control fields are generated within the RISC processor to enable the communication of scalar (32-bit) values across the processor—coprocessor interface. Another issue of great importance for the performance of a pipelined processor is the proper bypassing of operands flowing down the processor pipeline stages to the instruc- tion currently being decoded. Due to the adoption of a normally-illegal opcode, both the decoding and the bypassing logic itself had to be modified in order to enable VLSI Macrocell results Vector processo rimplementation campaign Fig. 17. Processor—Coprocessor VLSI layout of RAM-based VRF configuration with functional block overlay. Fig. 18. Synthesis/power estimation campaign of the parametric vector processor.
