Vedic Technology

Abstract—Wireless sensor network have several constraints, such as a short transmission range, poor processing capabilities, limited available power and slow execution time. The design of algorithms for fast processing of information in sensor network is an emerging research ...

The computational complexity of various data processing applications is vastly reduced when signals are represented in the frequency domain. Fourier analysis converts a signal from its original domain to a representation in frequency domain. In launch vehicle systems, FFT is required for telemetry data processing applications. Since the systems work in real time, a fast and efficient computation of the FFT is called for. Vedic mathematics based on ancestral Indian Vedas gives a different multiplication algorithm to carry out fast multiplication. The idea for designing the multiplier unit is adopted from ancient Indian mathematics "Vedas". The Urdhva-Tiryakbhyam sutra (method) was selected for implementation since it is applicable to all cases of multiplication. DSP applications essentially require the multiplication of binary floating point numbers. The IEEE 754 standard provides the format for representation of Binary Floating point numbers. Vedic Multiplication Technique...

Wireless sensor network have several constraints, such as a short transmission range, poor processing capabilities, limited available power and slow execution time. The design of algorithms for fast processing of information in sensor network is an emerging research area nowadays. However, due to unique characteristics of the sensor network computing paradigm, the objective is to design algorithms that meet two contradicting goal of low power and fast execution time. In this work, a power-time efficient algorithm is proposed which is implemented with the help of Vedic mathematics for computing FFT (Fast Fourier Transform) over data distributed across smart sensors. The word “Vedic” is derived from the word “veda” which means the store-house of all knowledge. Vedic mathematics is mainly based on 16 Sutras (or aphorisms) dealing with various branches of mathematics like arithmetic, algebra, geometry etc. Significant reduction in power requirement and delay has been achieved based on t...

Many “Digital Signal Processing” applications uses “fast fourier transform”. Common practice is to run FFT on Digital signal processor or Application specific IC. In this paper 8 point FFT is implemented using Radix 2 butterfly method. 3 stage pipelining is used to speed up the processing. Complex multiplication is done by incorporating complex Vedic multiplier which further enhances the speed.

Vedic mathematics or ancient mathematics is a unique technique of calculations based on 16 sutras. It provides an innovative way of computation of almost all the mathematical operations. In this era of digitization, engineers are working on increase speed of the digital circuits while reducing the size and power consumed. Arithmetic operations are the basic units of all the digital circuitry and hence optimizing these unit increases efficiency of the entire digital design. Unlike conventional mathematics, Vedic math provides different techniques to compute basic arithmetic operations. Vedic math reduces the computational steps required to achieve the result. Designers have implemented many computer architectures based on Vedic math. In this paper we review these architectures as well as several extended work in the area. In addition, we also review several state-of-art applications that take full advantage of such simple ancient Vedic Mathematical technique.

Most confusion has happened in understanding Vedic knowledge . It's major reason is not getting the terminology . Most sanskrit words in vedic literature have Dhatvarthak meaning ie meaning for particular function . They are not common names . Same name can be used in different fields . This paper gives light to understand these terms correctly

Cardiac vascular is a disease which plays a high risk factor in the world, where many people leads to death due to sudden cardiac arrest. Doctor uses several test to detect the factors that put people at high risk in this has more delay, which takes much time in computation due to the presence of multiplier in it. Thus to increase the speed of FFT the modified booth algorithm is proposed here, in which the number of slice, number of 4-input LUTs and number of bonded IOB gets reduced when compare to the other existing FFT speed increment algorithm, which is further implement in that recently proposed method of ECG analyzer and the output will be compared to find the efficiency.

Cardiac vascular is a disease which plays a high risk factor in the world, where many people leads to death due to sudden cardiac arrest. Doctor uses several test to detect the factors that put people at high risk in this has more delay, which takes much time in computation due to the presence of multiplier in it. Thus to increase the speed of FFT the modified booth algorithm is proposed here, in which the number of slice, number of 4-input LUTs and number of bonded IOB gets reduced when compare to the other existing FFT speed increment algorithm, which is further implement in that recently proposed method of ECG analyzer and the output will be compared to find the efficiency.

— The ever increasing demand for high speed, lighter, smaller & portable electronics directly translates to low power requirements. The designers are working on to reduce the size, execution time and power consumed by the processor. To increase the speed of any processor, the speed of ALU (arithmetic and logic unit) has to be increased. Arithmetic and logic unit is a fundamental building block of CPU which is a digital circuit that performs integer arithmetic and logic operations. The speed of the Arithmetic and logic unit depends on multipliers and adders. With the help of Veda ganitha, we can reduce the execution time, area, complexity and power requirement of an ALU. Veda Ganitha is an ancient technique, which simplifies multiplication, divisibility, operation on complex numbers, cubing, squaring, and square and cube roots. Veda ganitha is unique technique of calculations based on sixteen sutras (aphorisms) and thirteen sub sutras (corollaries). In this paper we propose to implement Urdwa tiryagbhyam, Nikhilam navatascharamam dasatah, Anurupyena, Dwanda yoga, Anurupye Veda ganitha sutras and analyze its performance by comparing with the conventional mathematics methods. By employing these Veda ganitha sutras in the computation algorithms of the ALU, the complexity, execution time, area, power etc can be reduced. In this work, Verilog HDL has been used to code the algorithms. Logic synthesis and simulation are done in Xilinx 12.2 and Xilinx ISE Simulator. Speed grade is-4. Synthesis results are compared to conventional method.

Fast Fourier Transform is an essential data processing technique in communication systems and DSP systems. Here, we propose high speed and area efficient 64-point FFT processor using Vedic algorithm. To reduce computational complexity and area, we develop FFT architecture by devising a Radix-4 algorithm and optimizing the realization by Vedic algorithm. Furthermore, it can be used in decimation in frequency (DIF) and decimation in time (DIT) decompositions. Moreover, the design can achieve very high speed, which makes them suitable for the most demanding applications of FFT. Indeed, the proposed Radix-4 Vedic algorithm based architecture requires fewer hardware resources. The synthesis results are same as that of theoretical analysis and it is observed that more than 15% reduction can be achieved in terms of slices count. In addition, the dynamic power consumption can be reduced and speed can be increased by as much as 16% using Vedic algorithm.

All of us know that ALU is a module which can perform arithmetic and logic operations. The reason behind choosing this topic as a research work is that, ALU is the key element of digital processors like as microprocessors, microcontrollers, central processing unit etc. Every digital domain based technology depends upon the operations performed by ALU either partially or whole. That’s why it highly required designing high speed ALU, which can enhance the efficiency of those modules which lies upon the operations performed by ALU. The speed of arithmetic is of extreme importance and depends greatly on the speed of multiplier. Therefore the technologies are always looking for new algorithm and hardware so as to implement this operation in much optimized way in the terms of area and speed. Vedic Mathematics deals with various branches of mathematics like arithmetic, algebra, geometry etc in computation algorithm of the coprocessor which will reduce the complexity of execution time, area and power consumption etc. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier. In this paper arithmetic logic unit is design with the pipelining technique based on vedic mathematics to improve the execution speed and consuming power.

Vedic mathematics or ancient mathematics is a unique technique of calculations based on 16 sutras. It provides an innovative way of computation of almost all the mathematical operations. In this era of digitization, engineers are working on increase speed of the digital circuits while reducing the size and power consumed. Arithmetic operations are the basic units of all the digital circuitry and hence optimizing these unit increases efficiency of the entire digital design. Unlike conventional mathematics, Vedic math provides different techniques to compute basic arithmetic operations. Vedic math reduces the computational steps required to achieve the result. Designers have implemented many computer architectures based on Vedic math. In this paper we review these architectures as well as several extended work in the area. In addition, we also review several state-of-art applications that take full advantage of such simple ancient Vedic Mathematical technique.

A fresh and original translation from Sanskrit of the dashrajnya hymn (hymn 7.18 of Rig Veda) describing this defining battle between Aryan king Sudas and his Aryan as well as non-Aryan foes. The decisive battle led to the uprooting of many tribes from the Sapta Sindhu area.

Many existing beliefs are shown to be merely due to misunderstandings. Further, it is shown that the existing translations fall well short of the true meaning.
For example, no Matsya tribe was involved in this battle.

Vedic Mathematics is the ancient methodology of Indian mathematics, which has a unique technique of calculations based on 16 Sutras (Formulae). A high speed complex multiplier design and FFT application of it using Vedic Mathematics is presented in this paper. The idea for designing the multiplier and adder/subtractor unit is adopted from ancient Indian mathematics "Vedas". On account of those formulas, the partial products and sums are generated in one step which reduces the carry propagation from LSB to MSB. The ever increasing demand in enhancing the ability of processors to handle the complex and challenging processes has resulted in the integration of a number of processor cores into one chip. Still the load on the processor is not less in generic system. This load is reduced by supplementing the main processor with Co-Processors, which are designed to work upon specific type of functions like numeric computation, Signal Processing, Graphics etc. The speed of FFT depends greatly on the multiplier. This work is carried out on xilinix platform usig HDL programming.comparing with the conventional multiplier 50% of the slices are reduced for the vedic multipliers.

Multiplier is one important block in the digital signal processor, computer. There are various multiplier
architectures are present, but in that simple multiplication is done using vedic mathematics through vedic multiplier. Vedic
multiplier uses vedic mathematics such as Urdhva Triyakbhyam and Nikhilam sutra. Using that multiplier we have low
power consumption, low delay and high speed. Which has become one of the important key area in VLSI design using
CMOS challenging technology.

New telecommunication systems are based more than ever before on digital signal processing. High speed digital telecommunication systems such as OFDM and DSL need real-time high-speed computation of the Fast Fourier Transform. Thus there is a need of innovative algorithms to improve the speed .In this paper, we propose vedic algorithm for the implementation of multipliers to be used in the FFT. Vedic mathematics (VM) comes with the simplest and effective algorithm for solving any typical engineering problem standing on the pillars of the "Vedic" principles. The conventional multiplication method requires more time & area on silicon than vedic algorithms. More importantly processing speed increases with the bit length. This will help ultimately to speed up the signal processing task, as it is well known that the multiplier is the basic building block of FFT. The VM has been synthesized for the target device 5vlx30ff324-3.