Programmable Logic

The paper focuses on the study of the checkability of digital circuits in relation to FPGA (Field Programmable Gate Array) components of safety-related systems that serve high-risk facilities, maintaining their functional safety in synergy with its own. Functional safety breaches are associated with failures that stimulate the use of fault-tolerant solutions. However, the possibilities of these solutions are limited by the number of failures which can be countered. As a result, functional safety, based only on circuit fault tolerance, faces the problem of multiple failures. This problem manifests itself in the example of hidden faults, which can be accumulated in significant quantities during extended normal operation of the system. The multiple manifestations of these faults in emergency mode call into question the fail-safety of fault-tolerant circuits, including FPGA components, which can accumulate faults in the memory of the LUT units. Ensuring the fail-safety of circuits requires taking into account their checkability, which depends on the data arriving at the inputs of the circuit in normal and emergency modes. A method for assessing checkability, which is important for the fail-safety of FPGA components, is proposed. Checkability is assessed on real input data, the change of which often extends only over a part of the range of values related to the normal functioning of the system. The method makes it possible to evaluate the change in the checkability of the circuit depending on the change in its input data.

A novel approach to Petri net modelling of Programmable Logic Controller (PLC) programs is presented. The modelling approach is a simple extension of Elementary Net Systems and a graphical design tool that supports the use of this modelling approach is provided. A key characteristic of the model is that the binary sensory inputs and binary actuation outputs of the PLC are explicitly represented. This leads to two improvements: outputs are unambiguous, and interaction patterns are more clearly represented in the graphical form. Use of this modelling approach produces programs that are simple, light-weight, and portable. The approach is demonstrated by applying it to the development of a control module for a MonTech Positioning Station.

Many reconfigurable architectures offer partial dynamic configurability, but current system-level tools cannot guarantee feasible implementations when exploiting this feature. We present a physically aware hardware-software (HW-SW) scheme for minimizing application execution time under HW resource constraints, where the HW is a reconfigurable architecture with partial dynamic reconfiguration capability. Such architectures impose strict placement constraints that lead to implementation infeasibility of even optimal scheduling formulations that ignore the nature of these constraints. We propose an exact and a heuristic formulation that simultaneously partition, schedule, and do linear placement of tasks on such architectures. With our exact formulation, we prove the critical nature of placement constraints. We demonstrate that our heuristic generates high-quality schedules by comparing the results with the exact formulation for small tests and a popular, but placementuanaware scheduling heuristic for larger tests. With a case study, we demonstrate extension of our approach to handle heterogenous architectures with specialized resources distributed between general purpose programmable logic columns. The execution time of our heuristic is very reasonable-task graphs with hundreds of nodes are processed in a couple of minutes.

In order to take into account physical design effects, a designer needs a feedback mechanism during interactive data path synthesis. In this paper, we propose a hypergraph model and a back-annotation algorithm which provide a feedback mechanism for back-annotation from physical designs to behavioral descriptions. Given a control-data flow graph and its structural design, this back-annotation technique can not only evaluate the design quality but can also feedback the delay to each edge and node in the graph. Therefore, a designer can identify the critical paths and improve the design. The hypergraph model and the back-annotation algorithm allow us to bridge the gap between the behavioral description and the physical design.

Embryonics (embryonic electronics) is a research project which attempts to draw inspiration form the world of biology to design better digital computing machines, and notably massively parallel arrays of processors. In the course of the development of our project, we have realized that the use of programmable logic circuits (field-programmable gate arrays, or FPGAs) is, if not indispensable, at least extremely useful. This article describes the main concepts of Embryonics and some of the peculiar features of the FPGA we designed to efficiently implement our embryonic machines. More particularly, we overview the mechanisms taken from the world of biology and how we brought them in the world of silicon.

Protection for installations that have been modernized or retrofitted presents a unique mix of problems that require a different perspective from a new installation. The paper addresses lightning, transients, and radiation that cause problems on programmable logic controllers, distributed control systems, and remote electronic transducers. While complex grounding grids and networks were not required for analog systems, newer digital equipment requires a very effective means of maintaining equal potential throughout the facility. Methods of protecting circuits include a variety of sophisticated and not-so-elegant techniques. Special consideration must be given to the impact that towers have on a protection system. The investigation ranges from no air terminals to lightning arrays. The protection problem is compounded when different soils such as clay and rock are encountered. Methods of calculating the grounding circuit resistance are identified. Although the paper is based on a retrofit, the techniques are appropriate for any industrial installation using distributed control.

We propose Reduced Voltage Swing (RVS) signaling (by elevating the logic 0 voltage) as opposed to Low Voltage Swing (LVS) signaling (which reduces the logic 1 voltage). We propose an inverter which generates RVS signals, and an extension with programmable logic for adjusted logic 0 voltage. The proposed RVS scheme achieves reduced active power consumption, minimum performance degradation and minimum area overhead (without extra power supply network and a minimum number of extra transistors). Application of multi-threshold voltage design further alleviates compromises on noise margin and leakage. Experimental results based on SPICE simulation show that RVS clocking achieves an average of 37% active power consumption reduction, 8% performance degradation.

The capability to rapidly execute the power flow (PF) calculations permit engineers in assured with stay bigger assured within the dependability, protection, and economical operation of their system within the case of planned or unplanned instrumentality failures. The purpose of this work is to investigate the use of FPGA characteristics to speed up power flow computing time for the on-line monitoring system of a power system. The work comprises which is the development of the Power flow program using the Fast-decoupled method based on FPGA (Field Programmable Gate Array), and LABVIEW (graphical programming environment). The program delivered very satisfactory results to solve a 30-bus test system. These findings suggest that in general that differences between the proposed work and the conventional fast decoupled method are satisfactory. As for the execution time, because the FPGA uses parallel solutions, the performance of the proposed method is faster. Also, the engagement of the FPGA and the LabVIEW program presented an effective monitoring system for observing the power system.

The paper describes the problems associated with the phenomena of metastability in clock edge-triggered flip-flop designs in PLD (Programmable Logic Devices) architecture. The metastability probability, which is dependent on functionality speed, characteristics of integrated circuit technology, design methodology and effects of environmental conditions is discussed. The evaluation of the MTBF (Mean Time Between Failure) characteristics of PLD is done, based on the propagation delay distribution measurement of bistable output in the circumstances of deliberately inducing metastable behaviour. The testing results help in design, examine and to predict required MTBF in logic circuits design targeted for PLD. The proper design methodology that would help to virtually overcome the metastability problem is discussed.

This paper concerns design and performance testing of an HDL module called SwaMURAy that is a configurable, high-speed data sequencing and flow control module serving as an intermediary between data acquisition (or pre-processing) and subsequent processing stages. While a FIFO suffices for many applications our case needed a more elaborate solution to overcome legacy design limitations. The SwaMURAy is designed around a system where a block of sampled data is acquired at a fast rate and is then distributed among multiple processing cores to achieve a desired processing rate; this pattern of processing is sometimes needed in software defined radio (SDR) and radio astronomy applications. This solution was partly in response to legacy design restrictions of the SDR platform used, a difficulty likely experienced by many developers whereby new sampling peripherals are inhibited by legacy characteristics of the underlying reconfigurable platform. Our SDR platform has a planned lifetime of at least five years; a complete redesign and re-fabrication would be too costly. While the SwaMURAy overcame some performance problems, other problems arose. This paper overviews the SwaMURAy design, performance improvements achieved in a SDR case study, and remaining limitations and workarounds we expect will achieve further improvements.

Autonomous systems are designed and deployed in different modeling paradigms. These environments focus on specific concepts in designing the system. We focus our effort in the use of cognitive architectures to design autonomous agents to collaborate with humans to accomplish tasks in a mission. Our research focuses on introducing formal assurance methods to verify the behavior of agents designed in Soar, by translating the agent to the formal verification environment Uppaal.

The CPU Design Kit is a prototyping platform designed at University of California, Santa Cruz, for teaching the Processor Design class. The prototyping platform allows the design and implementation of a 32-bit pipelined CPU. The prototyping hardware consists of an ISA-bus-based printed-circuit board containing six Altera FLEX EPF81500 programmable logic chips providing a total of 80,000 usable gates, static RAM chips to implement register file and caches, and hardware support for monitoring and debugging. A Windows-based user interface provides access to the necessary software tools for downloading designs into the board, debugging, and control of the CPU.

NSLS-II, the successor to NSLS (National Synchrotron Light Source) at Brookhaven National Lab, is scheduled to be open to users worldwide by 2015 as a world-class advanced synchrotron light source because of its unique features: its half-mile-circumference (792 m) Storage Ring provides the highest beam intensity (500 mA) at medium-energy (3 GeV) with sub-nm-rad horizontal emittance (down to 0.5 nm-rad) and diffraction-limited vertical emittance at a wavelength of 1 Å (<8 pm-rad). As the eyes of NSLS-II accelerators to observe fascinating particle beams, beam diagnostics and controls systems are designed to monitor and diagnose the electron beam quality so that NSLS-II could be tuned up to reach its highest performance. The design and implementation of NSLS-II diagnostics and controls are described. Preliminary commissioning results of NSLS-II accelerators, including Linac, Booster, and Storage Ring, are presented. INTRODUCTION The construction of NSLS-II (NSLS-2) began in Mar. 20...

This paper presents a literature survey for technology mapping algorithm in field-programmable gate array architectures with single, dual and multiple supply voltages (Vdds) for power optimization , included both dynamic and leakage power reduction, interconnect power and power gating. To carry out this work, we first discuss a single-Vdd model on FPGA, based on LUT based technology mapping and clustering algorithm. And then, compare it with dual-Vdd mapping algorithm which can further improve for total power and delay minimization, named configurable dual-Vdd for FPGA. In addition, we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chip performance constraint. Therefore, this paper presents a detailed study for dynamic power, leakage power, interconnect power for FPGAs with different configuration logic blocks (CLBs), different interconnect strategies and different process...

A novel feedback current controller for three-phase load driven by power inverter is proposed. Main design specifications are robustness to load electrical parameters, fast dynamical response, reduced switching frequency, and simple hardware implementation. To meet previous specifications a multi-variable hysteresis type controller is proposed, designed as a finite-state automaton and implemented with a programmable logic device. After a general introduction, system analysis is performed, control targets are specified, and the proposed control strategy is presented and discussed. Further, actual controller architecture, based on simple analog-logic hardware, is shown and experimental results are presented using an induction motor as the inverter load. However, this does not limit the wider applicability of the proposed controller that is suitable for different types of three-phase ac loads. Conventions itals are matrices.

FPGA circuits are increasingly used in many fields: for rapid prototyping of new products (including fast ASIC implementation), for logic emulation, for producing a small number of a device, or if a device should be reconfigurable in use (reconfigurable computing). Determining if an ...

This project focuses on the design and simulation of Random Access Memory (RAM) and Read-Only Memory (ROM) modules using Verilog HDL. The RAM module supports read and write operations, while the ROM module allows only read operations with pre-initialized data. Both memory modules are designed to accommodate an 8-bit data width and handle up to 8 memory allocations. A comprehensive testbench was developed to verify the functionality of the RAM and ROM designs. The testbench simulates memory operations, including address selection, data read/write, and output validation. Simulation waveforms were analyzed to confirm the correct behavior of the memory modules. This project was implemented on EDA Playground, utilizing its simulation environment to debug and verify the design. The work provides a foundational understanding of digital memory design, Verilog HDL programming and simulation methods, with the potential for future expansion and integration into more advanced systems, including FPGA-based applications. The project successfully shows how RAM and ROM components can be efficiently modeled, tested, and validated using hardware description languages, contributing to the development of robust and scalable digital systems.

The Energy Recovery Linac Prototype (ERLP) is a 35 MeV superconducting linac currently being commissioned at Daresbury Laboratory. Its purpose is to demonstrate the technology necessary to design and build a 600 MeV energy recovery linac (4GLS), which, together with a suite of XUV, VUV, and IR FELs can be used to undertake pump-probe experiments to investigate dynamic systems. The ERLP control system is based on EPICS, VME64x hardware and the VxWorks operating system. Status control and interlock protection are handled by a Daresbury-designed CANbus system that has been tightly integrated into EPICS. Construction and commissioning of ERLP have taken place in parallel, and this introduced a number of problems in the planning and implementation of the control system. This paper describes the ERLP control system and discusses the successes and difficulties encountered during the early phases of commissioning. Plans are already in place to extend the control system to cover EMMA, a novel, nonscaling, fixed-field alternating gradient (FFAG) accelerator that will be added to ERLP in 2008/9.

This document describes the complete development of an embedded real-time application using the RTEMS (Real-Time Executive for Multiprocessor Systems) operating system on a PowerPC P2020 processor platform. The project was executed in a FreeBSD-based development environment and targets aerospace-grade performance and reliability. Objectives-Design a real-time system using RTEMS on PowerPC P2020.-Ensure deterministic execution, low latency, and fault tolerance.-Utilize open-source tools to reduce costs and increase transparency.-Implement robust communication protocols and drivers.

Increasing demands on electricity supply, with the need for system economic optimization and power system growth limitations, have a significant impact on power system reliability. Because of these system demands, the power system operates closer to its stability limits. When the system operates in extreme conditions, load shedding, generation shedding, or system islanding must occur to prevent total system collapse. Typical causes of system collapse are voltage instability or transient angle instability. These instabilities can occur independently or jointly. In most cases, system wide-area disruptions begin as a voltage stability problem. Because of a failure to take proper actions for the system to recover, this voltage stability problem evolves into an angle stability problem. New monitoring, protection, and communications technologies allow us to implement economical local-and wide-area protection systems that minimize risk of wide-area system disruptions or total system collapse. This paper provides examples of actual system disruptions and historical wide-area protection system (WAPS) solutions that use such traditional approaches as underfrequency and undervoltage load shedding. The paper also presents solutions that use programmable logic capabilities, faster communications, and synchronized phasor measurements available in meters and protective relays to prevent system disruptions.

Programmable Logic Controllers (PLCs) play a significant role in the control of production systems and Sequential Function Chart (SFC) is one of the main programming languages. The reaction time of a PLC is a fundamental matter in discrete event control systems. We will show that the reaction time of PLC depends greatly on the SFC structure, on the events sequence and also on the algorithm that executes the SFC. Five algorithms have been analyzed: Brute Force, Enabled Transitions, Representing Places, Deferred Transit and the Immediate Transit evolution models. The analysis has been carried out over a SFC library composed by well known models which can be scaled using a parameter. Finally we propose a new SFC execution technique adapted to efficiently execute a subclass of SFCs. We call this technique the Active Steps Algorithm.

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Placement process is one of the vital stages in physical design. In this stage, modules and elements of the circuit are placed in distinct locations based on optimizationprocesses. Hence, each placement process influences one or more optimization factor. On the other hand, it can be statedunequivocally that FPGA is one of the most important and applicable devices in our electronic world. So, it is vital to spend time forbetter learning of its structure. VLSI science looks for new techniques for minimizing the expense of FPGA in order to gain better performance. Diverse algorithms are used for running FPGA placement procedures. It is known that particle swarm optimization (PSO) is one of the practical evolutionary algorithms for this kind of applications. So, this algorithm is used for solving placement problems. In this work, a novel method for optimized FPGA placement has been used. According to this process, the goal is to optimize two objectives defined as wire length and overlap removal functions. Consequently, we are forced to use multi-objective particle swarm optimization (MOPSO) in the algorithm. Structure of MOPSO is such that it introduces set of answers among which we have tried to find a unique answer with minimum overlap. Itis worth noting that discrete nature of FPGA blocks forced us to use a discrete version of PSO. In fact, we need a combination of multi-objective PSO and discrete PSO for achieving our goals in optimization process. Tested results on some of FPGA benchmark (MCNC benchmark) are shown in "experimental results" section, compared with popular method "VPR". These results show that proper selection of FPGA's size and reasonable number of blocks can giveus good response.

The security of the Internet can be improved using Programmable Logic Devices (PLDs). A platform has been implemented that actively scans and filters Internet traffic for Internet worms and viruses at multi-Gigabit/second rates using the Field-programmable Port Extender (FPX). Modular ...

In presenting this dissertation in partial fulfillment of the requirements for the doctoral degree at the University of Washington, I agree that the Library shall make its copies freely available for inspection. I further agree that extensive copying of the dissertation is allowable only for scholarly purposes, consistent with "fair use" as prescribed in the U.S. Copyright Law. Requests for copying or reproduction of this dissertation may be referred to Proquest Information and Learning, 300 North Zeeb Road, Ann Arbor, MI 48106-1346, to whom the author has granted "the right to reproduce and sell (a)

This paper presents a methodology for efficient measurement of digital broadcasting signals, both with field trials or at the laboratory. The study is focused on measuring the C/N requirement for achieving a threshold BER. A comparison between the traditional techniques and the proposed methodology is analyzed in this work. The key of the methodology presented in this paper is the use of general purpose equipment such as a vector signal analyzer for recording baseband IQ samples.

In this paper, a method for the generation of RF reference signals for synchrotrons and storage rings will be presented. With these reference signals, the RF cavities in the Facility for Antiproton and Ion Research (FAIR) shall be synchronised. Digital frequency generators that work according to the DDS (direct digital synthesis) principle will be used as reference generators. Via an optical network with star topology, these reference generators will be fed with two clock signals that show a certain correlation of frequency and phase. Due to delay measurements, their phases at different end points of the optical network are known. From these clock signals, reference signals with specific frequencies can be derived. The phases of these reference signals can be finetuned against the phases of the clock signals, allowing the phases of different reference signals to be synchronised. With the commercially available DDS generators used in the prototype, phase steps of 0.022° are possible. At a reference signal frequency of 50 MHz, this corresponds to 1.22 ps. The presentation describes the functionality of this method for reference signal generation and shows under which conditions the step size of the phase adjustment can be improved further.

Measurement of power supply for design of experimental cyclotron in Yogyakarta (DECY-13), i.e. RF-generator 77.78 MHz, especially driver amplifier as important part, has been carried out, in order to minimize the reflected power. Starting from direct digital synthesizer (DDS) as exciter of the radio frequency (RF) wave, having power up to 20 W, the signal sent then to the driver, that has an amplifying factor of around 50. Output of driver works as input for final power of designed DECY-13, which needs about 10 kW of RF power supply for operating the cyclotron. Using network analyzer to get the best position of the RF-power-coupler, it was found the value of dee impedance equals to (50.9-j0.3) Ω. The signal detected has the behavior as capacitively having value of around 6 nF, that showed by smith chart. An output of 0.8 W by DDS has resulted of 300W to the driver. By a pure resistance 50 Ω dummy load, the system can achieve final power of almost 10 kW.

The importance of cryptography applied to security in electronic data transactions has acquired an essential relevance during the last few years. In this work, an FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is proposed. The proposed design is developed on a soft-microcontroller (Microblaze) using hardware descriptive language (especially Verilog), Xilinx EDK environment. All the results are synthesized and simulated using Xilinx EDK, Xilinx ISE and ISim software respectively. An iterative looping methodology of block and key size of 128 bits is approached and also, S-box lookup table implementation is carried out which gives low latency, low complexity architecture and high throughput. The simulation results show the performance of the design.

The Linux Operating System is used by a wide range of companies, mainly due to its security and stability. The latest FPGA devices, with embedded processors, allow the development of SoCs running this OS. One of the key features of FPGAs is their ability to change the hardware architecture while the system is running. It is possible to reconfigure one or more regions of the FPGA while the remainder continues to work. These partially reconfigurable regions inside the FPGA can be used to implement software functions, accelerating the execution time for the system. This work presents an FPGA system that provides the required interfaces to deploy Linux bash commands mapped directly into partially reconfigurable blocks of the FPGA. These commands can be executed in any order, thanks to a hardware interface, equivalent to the software pipe interface in Linux, implemented on the static region of the FPGA. The methodology presented in this paper allows the hardware implementations of comman...

The paper deals with designing finite state machines (FSM) by Nano PLA structures. Due to the devicemissing domination in nano-structures, it is desired to minimize both the area and the number of PLA devices required for the FSM implementation. We propose a solution of the minimization problem. Our solution is based on: a) partition of the FSM for two interacting components; b) transformation of one or two of the component FSMs into a dense form. We show that combining the above techniques provides a significant ...

A phase-lock loop tune measurement system was commissioned during the RHIC2001 run. One meter long 50 ohm striplines in each of the planes of both of the RHIC rings were driven at 239MHz with about 1 watt of power. The pickups are 22cm long ...

– The paper reports the tests conducted on a dedicated Transducer Independent Interface (TII) to check its compliance with standard IEEE 1451.2 specifications. The interface was built using a synchronous data transfer based on the Serial Peripheral Interface (SPI) protocol ...

This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Through a coupling of compile-time analysis routines and hardware synthesis tools, we automatically configure a given set of the hardware-programmable functional units (PFUs) and thus augment the base instruction set architecture so that it better meets the instruction set needs of each application. We refer to this new class of general-purpose computers as PRogrammable Instruction Set Computers (PRISC). Although similar in concept, the PRISC approach differs from dynamically programmable microcode because in PRISC we define entirely-new primitive datapath operations. In this paper, we concentrate on the microarchitectural design of the simplest form of PRISC-a RISC microprocessor with a single PFU that only evaluates combinational functions. We briefly discuss the operating system and the programming language compilation techniques that are needed to successfully build PRISC and, we present performance results from a proof-of-concept study. With the inclusion of a single 32-bit-wide PFU whose hardware cost is less than that of a 1 kilobyte SRAM, our study shows a 22% improvement in processor performance on the SPECint92 benchmarks.

While neural networks are good at learning unspecified functions from training samples, they cannot be directly implemented in hardware and are often not interpretable or formally verifiable. On the other hand, logic circuits are implementable, verifiable, and interpretable but are not able to learn from training data in a generalizable way. We propose a novel logic learning pipeline that combines the advantages of neural networks and logic circuits. Our pipeline first trains a neural network on a classification task, and then translates this, first to random forests, and then to AND-Inverter logic. We show that our pipeline maintains greater accuracy than naive translations to logic, and minimizes the logic such that it is more interpretable and has decreased hardware cost. We show the utility of our pipeline on a network that is trained on biomedical data. This approach could be applied to patient care to provide risk stratification and guide clinical decision-making.

The challenge of extending Moore's Law past the physical limits of the present semiconductor technology calls for novel innovations. Several novel nanotechnologies are being proposed as an alternative to their CMOS counterparts, with nanowire crossbar being one of the most promising paradigms. Quite recently, a new promising clock-free architecture, called the Asynchronous Crossbar Architecture has been proposed to enhance the manufacturability and to improve the robustness of digital circuits by removing various timing related failure modes. Even though the proposed clock-free architecture offers several merits, it is not free from the high defect rates induced due to nondeterministic nanoscale assembly. In this work, a unique Functional Test Algorithm (FTA) has been proposed and validated to test for manufacturing defects in this architecture. The proposed Functional Test Algorithm is aimed at reducing the testing overhead in terms of the time and space complexity associated with the existing sequential test scheme. In addition, it is designed to provide high fault coverage and excellent fault-tolerance via post-reconfiguration. This test scheme can be effectively used to assure true functionality of any threshold gate realized on a given PGMB. The main motivation behind this research is to propose a comprehensive test scheme which can achieve sufficiently high test coverage with acceptable test overhead. This test algorithm is a significant effort towards viable nanoscale computation. This work has been organized into three papers, explaining the proposed algorithm, demonstrating its working, describing the achievable replacement schemes using the proposed tool and providing a performance evaluation metric specifically proposed to evaluate the functional test algorithm. v ACKNOWLEDGEMENTS First and foremost, I would like to thank Almighty God for providing me with all the good health, strength and knowledge to complete my thesis and masters. I would like to express sincere gratitude and heartfelt thanks to my advisor Dr. Minsu Choi for his guidance, encouragement and invaluable contributions throughout my graduate study as well as in completing this research. I would also like to thank him for providing me with financial support during my master's study. To my committee members, Dr. Sahra Sedigh and Dr. Theodore McCracken, I extend my deepest appreciation and thanks for their time and effort in serving as committee members and reviewing this dissertation. My sincere thanks to Dr. V A Samaranayake of Mathematics and Statistics department for his important inputs. Special thanks to Ravi Bonam and Shikha Chaudhary, senior research members of Dr.Choi's research group for their help and ideas. Thanks go to my friends and roommates for all the happy times and memorable moments we shared. Lastly, but most importantly, I am indebted to my parents, my mother aunt for their unparallel love and patience with me during my endeavors. Without special support and motivation from my uncles, aunt and love from my brothers, Srihari, Varun, Karthik and young sister Vaishnavi, grandparents and all my close relatives and friends back in India, I would not have been able to reach this stage of life. vi

Measurement of power supply for design of experimental cyclotron in Yogyakarta (DECY-13), i.e. RF-generator 77.78 MHz, especially driver amplifier as important part, has been carried out, in order to minimize the reflected power. Starting from direct digital synthesizer (DDS) as exciter of the radio frequency (RF) wave, having power up to 20 W, the signal sent then to the driver, that has an amplifying factor of around 50. Output of driver works as input for final power of designed DECY-13, which needs about 10 kW of RF power supply for operating the cyclotron. Using network analyzer to get the best position of the RF-power-coupler, it was found the value of dee impedance equals to (50.9 - j0.3) Ω. The signal detected has the behavior as capacitively having value of around 6 nF, that showed by smith chart. An output of 0.8 W by DDS has resulted of 300W to the driver. By a pure resistance 50 Ω dummy load, the system can achieve final power of almost 10 kW.

It is presented, in this paper, a methodology that can be applied since the definition of the specifications set for the behaviour of an automation system until the complete implementation of the system controller. For this, it is used the GEMMA for the controller structure, the SFC for the controller specification, the Automation Studio software for the controller simulation and Timed Automata and UPPAAL software for the controller Formal Verification. The application of the related methodology is shown on a case study based on an Automated Production Line and the obtained results are extrapolated for other systems of the same type.

This paper discusses the design of a digital programmable logic circuit to produce a 5 V-output square wave pulses for four high power MOSFET switches using a fixed PWM circuit. It will be applied to drive the synchronous rectifier buck converter (SRBC) circuit. The PWM signals with multiple fixed time delay of 15 ns, 232 ns, 284 ns and 955 ns are generated. The steps taken to analyze each propagation time delay of each logic gate used and its combination are carefully studied. A multiplexer is added at the output of the logic circuit to select and produce the desired output pulses of 20 % duty ratio. The logic outputs are compared with the analog pulses and results match each other within 1 % in difference.

Abstract-An innovative laboratory methodology for the digital design introductory course is presented. We replace the traditional lab experiences, where students have to come to school classrooms, with a “lab at home” concept. More than 65 kits with a programmable ...

WebLab-Deusto is a learning environment used at the University of Deusto as the landing platform to several remote laboratories currently used in high school and university level courses. One of these remote labs is VISIR, a remote electricity kit that can be used in teaching DC and AC circuits. As happens in any openended educational environment, it is difficult to assess the learning effects of this tool. Fortunately the communication between the users and the VISIR remote lab in the WeblabDeusto leaves behind a set of log information that can be analyzed. This contribution presents our current work-in-progress in analyzing these logs for better understanding the learning processes that take place when using this remote lab.

An Electric Propulsion System (EPS) uses electrical energy to change the velocity of a spacecraft.EPS configuration consists of a thruster module, feed system and power processing and control system. In this paper designing the Data Acquisition system (DAS) and various Interface interfaces for Telecommand and Telemetry systems for controlling different element of EPS. The necessary control signals are designed and implemented using IP CORE 86 in Libero software.

The purpose of this work is to introduce two fault tolerant architectures for application in the mecatronics systems control, which require operation reliability and availability. The unit of processing in one of the architectures was the PIC 16F84A, and in another it was used the Basic Step 2K. Both the architectures are composed by three identical modules, which they communicate by means of protocols implemented by programming. They are able of detect faults in a module, of transparent way to the application. Or in another words, without interference or interruption in the control task. In both the architectures, in case of fault in a module, they can be left for maintenance and afterwards reintegrated to the system, without implying in the idleness of the controlled mecatronic system. Details on the differences and similarities between both architectures, characteristics of the hardware and software projects, as well as considerations about its performances, they are boarded alon...

Network routers rely on content addressable memories (CAMs) to accelerate the process of looking up the next hop of a packet. The input for this lookup is the destination address of the packet. This article describes our implementation and evaluation of a versatile prototype for a CAM. This prototype allows the empirical evaluation of the idea of caching lookup results in a multizone cache organized according to the length of the network prefix portion of the addresses. Implementing a cache in an FPGA efficiently required the design of a new cache replacement policy, the Bank Nth Chance policy. In this article we present results from a functional simulator that allows the comparison of this new policy with existing ones such as least recently used, first in, first out and Second Chance. With a complete and functional prototype in a Xilinx Virtex 2000E device, we also report frequency of operation and occupation of the device. We present programmable logic design techniques that enable the implementation of ternary logic CAM cells, the efficient implementation of the new policy reference fields, and the pipelining of lookups.

This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) binary images. Its processing function is determined by a reduced set of 19 analog coefficients whose values are programmable with 7-b accuracy. The internal programming signals are analog, but the external control interface is fully digital. Onchip nonlinear digital-to-analog converters (DAC's) map digitally coded weight values into analog control signals, using feedback to predistort their transfer characteristics in accordance to the response of the analog programming circuitry. This strategy cancels out the nonlinear dependence of the analog circuitry with the programming signal and reduces the influence of interchip technological parameters random fluctuations. The chip includes a small digital RAM memory to store eight sets of processing parameters in the periphery of the cell array and four 2-D binary images spatially distributed over the processing array. It also includes the necessary control circuitry to realize the stored instructions in any order and also to realize programmable logic operations among images. The chip architecture is based on the cellular neural/nonlinear network universal machine (CNN-UM). It has been fabricated in a 0.8-m single-poly double-metal technology and features 2-s operation speed (time required to process an image) and around 7-b accuracy in the analog processing operations. Index Terms-Analog array processors, cellular neural networks, focal plane processors, vision chips. I. INTRODUCTION C ONVENTIONAL image-processing systems use a charge-coupled device (CCD) camera for parallel acquisition of the input image and serial transmission of the digitalized image to a separate processing element. It results in huge data rates which conventional computers are not capable of analyzing in real-time. For instance, a color 512 512 pixel camera delivers about 20 MB/s, for Manuscript

Embryonics घembryonic electronicsङ is a research project that attempts to draw inspiration form the world of biology to design better digital computing machines, and notably massively parallel arrays of processors. In the course of the development of our project, we h a ve realized that the use of programmable logic circuits घaeeld-programmable gate arrays, or FPGAsङ is, if not indispensable, at least extremely useful. This article describes some of the peculiar features of the FPGA we designed to eaeciently implement our embryonic machines. More particularly, we discuss the issues of memory storage and of self-repair, critical concerns for the implementation of our bio-inspired machines.

Possible switching architectures, with Optically Programmable Logic Cells-OPLCs-will be reported in this paper. These basic units, previously employed by us for some other applications mainly in optical computing, will be employed as main elements to switch optical communications signals. The main aspect to be considered is that because the internal components of these cells have nonlinear behaviors, namely either pure bistable or SEED-like properties, several are the possibilities to be obtained. Moreover, because their properties are dependent, under certain condition, of the signal wavelength, they are apt to be employed in WDM systems and the final result will depend on the corresponding optical signal frequency. We will give special emphasis to the case where self-routing is achieved, namely to structures of the Batcher or Banyan type. In these cases, as it will be shown, there is the possibility to route any packet input to a certain direction according to its first bits. The number of possible outputs gives the number of bits needed to route signals. An advantage of this configuration is that a very versatile behavior may be allowed. The main one is the possibility to obtain configurations with different kinds of behavior, namely, Strictly Nonblocking, Wide-Sense Nonblocking or Rearrangeably Nonblocking as well as to eliminate switching conflicts at a certain intermediate stages.

Digital chaotic behaviour in an Optically-Processing Element is analyzed. It was obtained as the result of processing two fixed train of bits. The process is performed with an Optically Programmable Logic Gate. Possible outputs, for some specific conditions of the circuit, are given. Digital chaotic behaviour is obtained, by using a feedback configuration. Different ways to analyze a digital chaotic signal are presented.