PHASE DETECTOR

The question of sample-clock quality is a perennial one for digital audio equipment designers. Yet most chip makers provide very little information about the jitter performance of their products. Consequently, equipment designers sometimes get burnt by jitter issues. The increasing use of packet-based communications and class-D amplification will throw these matters into sharp relief. This paper reviews various ways of characterizing and quantifying jitter, and refines several of them for audio purposes. It also attempts to present a common, unambiguous terminology. The focus includes wideband jitter, baseband jitter, jitter spectra, period jitter, long-term jitter and jitter signatures. Comments are made on jitter transfer through phase-locked loops and on the jitter susceptibility of audio converters.

The question of sample-clock quality is a perennial one for digital audio equipment designers. Yet most chip makers provide very little information about the jitter performance of their products. Consequently, equipment designers sometimes get burnt by jitter issues. The increasing use of packet-based communications and class-D amplification will throw these matters into sharp relief. This paper reviews various ways of characterizing and quantifying jitter, and refines several of them for audio purposes. It also attempts to present a common, unambiguous terminology. The focus includes wideband jitter, baseband jitter, jitter spectra, period jitter, long-term jitter and jitter signatures. Comments are made on jitter transfer through phase-locked loops and on the jitter susceptibility of audio converters.

We propose and demonstrate experimentally a method for the sensitive measurement of the relative timing jitter of two mode-locked lasers, which can be either free-running or timing-synchronized to a common reference oscillator. The method is based on the indirect comparison of the phases of two photodetector outputs, using a microwave oscillator, the noise of which does not affect the results, electronic mixers, and a sampling oscilloscope. We carefully analyze and experimentally demonstrate the potential of this method. Compared to phase detector methods, it has a broader scope of applications and a lower sensitivity to intensity noise. We also obtained data on the coupling of intensity to timing noise in photodetectors.

A compact acquisition system developed for a flexible large area monoport tactile surface is presented in this paper. This sensor requires a single port connection and avoids complicated matrix acquisition system and multiplexing. The tactile surface is based on a coplanar transmission line printed on a large area flexible substrate. Touching the waveguide generates a reflected signal. A harmonic analysis of this reflected signal at the line input port allows locating the touch event. A compact and low complexity acquisition system has been developed in order to demonstrate the principle and evaluate the feasibility of its integration on the sensor. Theoretical background, design and measurements on the overall sensor are exposed. The acquisition circuit imperfections have been demonstrated experimentally and correction methods have been proposed and implemented. Results are presented, and to assess the precision of the compact acquisition system, they are compared to reference measurements made with a Vector Network Analyzer.

We propose a scheme to generate broadband high harmonic supercontinuum and single attosec ond pulse emission in time domain by employing a chirped polarization gating laser field. It is shown that this scheme can significantly extend the high harmonic cutoff to higher energy region, and the produced isolated attosecond pulse is shorter than 100 attoseconds after proper dispersion compensation, when a 7 fs driving laser pulse is used.

Practical and theoretical limits on the bandwidth of distributed optical phase modulators and traveling-wave photodetectors are given. For the case of perfect velocity matching, RF transmission losses are the main performance-limiting factor. However, some highperformance modulators require highly-capacitive transmission lines making proper slowwave operation difficult to achieve.

Abstract: The design of frequency synthesizer, often implemented by a phase-locked loop (PLL), is a challenging task for RF designers in terms of power dissipation. In this paper an ultra-low power wide band 2/3 prescaler simulated by CEDEC 0.18 µm CMOS technology is presented. The proposed prescaler is capable of operating up to 8 GHz with smooth output waveform for divide-by-2 operation. Compared with concurrent extended true single phase clock (E-TSPC) circuits at supply voltage of 1.8 V, more than 50% reduction in total power ...

This paper describes a design of a fully digital clock and data recovery (CDR) system with plesiochronous clocking. Besides the well known advantages of digital implementations over analog ones in terms of robustness against process and temperature variations, scalability, compactness and low cost, the system also enjoys many features. It can withstand an input data cycle-to-cycle jitter up to ±37.5% UI. Data are obtained through digital correlation with the incoming symbol instead of ordinary sampling at the middle of the eye pattern, which improves BER. Furthermore, it needs only, at worst, three preamble bits to get into lock. It is insensitive to long runs of transition-free data patterns. The extracted data clock is not shifted as long as input data jitter is small (typically less than ±12.5%UI), thus, minimizing jitter in the extracted data clock. Besides, the extracted clock has a 50% duty cycle.

Zero Crossing Digital Phase Locked Loop with Arc Sine block (AS-ZCDPLL) is used to linearize the phase difference detection, and enhance the loop performance. The loop has faster acquisition, less steady state phase error, and wider locking range compared to the conventional ZCDPLL. This work presents a Zero Crossing Digital Phase Locked Loop with Arc Sine block (ZCDPLL-AS). The performance of the loop is analyzed under mobile faded channel conditions. The mobile channel is assumed to be two path fading channel corrupted by additive white Gaussian noise (AWGM). It is shown that for a constant filter gain, the frequency spread has no effect on the steady state phase error variance when the loop is subjected to a phase step. For a frequency step and under the same conditions, the effect on phase error is minimal.

The previous frequency synthesizer techniques for scalable SDR are not compatible with high end applications due to its complex computations and the intolerance over increased path interference rate which leads to an unsatisfied performance with improved user rate in real time environment. Designing an efficient frequency synthesizer framework in the SDR system is essential for 5G wireless communication systems with improved Quality of service (QoS). Consequently, this research has been performed based on the merits of fully digitalized frequency synthesizer and its explosion in wide range of frequency band generations. In this paper hardware optimized reconfigurable digital base band processing and frequency synthesizer model is proposed without making any design complexity trade-off to deal with the multiple standards. Here fully digitalized frequency synthesizer is introduced using simplified delay units to reduce the design complexity. Experimental results and comparative analyzes are carried out to validate the performance metrics and exhaustive test bench simulation is also carried out to verify the functionality.

Digital PLLs (DPLLs) have emerged as reliable alternatives to analog PLLs since they are more robust in the presence of process variations and mismatch and do not need a large on-chip capacitor to realize a loop filter. However, a DPLL employs a timeto-digital converter (TDC) to resolve the phase error in quantized steps which shows up as deterministic jitter in the output clock. Similarly, a DPLL tunes a digitallycontrolled-oscillator (DCO) in discrete frequency steps which adds an extra source of jitter. Furthermore, the quantized response of the DPLL may cause chaotic limit cycles in some configurations. This thesis presents innovations to make DPLLs suitable for a wide range of applications. First, a novel low-power TDC with 4 ps resolution, approximately an order of magnitude better than an inverter delay in the 0.13 µm CMOS technology, is enabled by employing a highly digital coarse-fine TDC with a calibrated coarse stage followed by a fine stochastic stage. On power-up, on-chip calibration algorithm based on a balanced mean code density test is used to minimize nonlinearities in the coarse TDC, reducing worst-case spurs from -54.4 dBc to -70.55 dBc at 1.995 GHz operation. The thesis also investigates dead-zone behavior in DPLLs caused by the quantiza-First and foremost I would like to express my sincere thanks and appreciation to my supervisor, Prof. Anthony Chan Carusone, for his guidance, support, and his constant encouragement throughout the course of this thesis. Many thanks to my thesis committee members, Prof. Glen Gulak, Prof. Antonio Liscidini, and Prof. Wai Tung Ng, for reviewing my thesis and for their valuable feedback. I would like to thank my external examiner, Prof. Michael Peter Kennedy, for his detailed and valuable feedback. To my colleagues and friends in BA5158 and BA5000 at the University of Toronto, thank you for encouragement and unforgettable moments. Special thanks for Karim Abdelhalim

Abstract—In this paper, the authors present a static frequency divider designed for the 24GHz ISM band, with a divide ratio of 16, using an innovative sensitivity matching concept between the first and the second stages. The divider is using a master-slave toggle flip-flop topology and implemented in a 0.8 µm SiGe HBT process with a maximum fT of 80 GHz. The circuit operates up to 25 GHz and consumes 240 mW at 4 V supply voltage.

Multiplier free Digital Phase-Locked Loop (DPLL) based on Hilbert transform has been analyzed in this paper. The performance of this DPLL when applied as FM demodulator is evaluated in relation to the DPLL with Multiplier based Phase Detector (MPD) showing better dynamic properties expressed in the form of the lock range, settling time, pull-out range etc.

Spallation-neutron facilities often use precisely-phased rotating choppers to parse the neutron beams that are used in various experiments. Typically, the reference signal is a digital pulse train of nearly-constant frequency. A chopper provides phase and frequency information to a controller by outputting a digital pulse each time its rotating blade passes a top-dead-center (TDC) location. Early controller designs used analog techniques to measure speed and phase and perform the necessary closed-loop control. More recently, purely digital techniques using digital signal processors (DSPs) and counter-based phase detectors have been implemented. This paper describes a relatively simple and low-cost method of implementing chopper speed and phase control with an off-the-shelf DSP card. In this technique, the reference and chopper-TDC digital-pulse trains are slewrate limited to form trapezoidal waveforms which are sampled by 16-bit ADCs on the DSP board. The DSP finds the zero crossings, computes the frequency and relative phase of the two input signals and performs the dual-loop feedback control functions. A 16-bit DAC outputs a control voltage to a chopper-motor power driver. The paper also describes the rate-limiting circuitry, the real-time dual-loop control algorithm, and system performance.

This thesis presents the theory and analysis of IF polar receiver (PRX) architecture. By using new quantization techniques in the polar domain, the proposed receiver can boost the signal to quantization noise ratio (SQNR) compared to a traditional rectangular (I/Q) receiver. The proposed PRX is composed of a magnitude and a phase quantizer. The magnitude quantizer is similar to the conventional rectangular quantizer in voltage domain. The phase quantizer employs a time-todigital converter (TDC) for phase detection. Furthermore, an intuitive graphical method is used to analyze the quantization properties of the polar quantization. A 10 bit polar quantizer is designed and fabricated in 130nm CMOS, and achieves 2-to 5-dB of SQNR improvement compared to rectangular quantizer for signal bandwidths as high as 20MHz.

In this paper, we consider nonlinear dynamics of a control circuit called phase-locked loop and provide a rigorous mathematical analysis to establish conditions under which the lock-in, pull-in, and hold-in ranges, which correspond to different types of system stability, coincide (the Viterbi problem). The analytical results are compared with both computer simulation and estimates of the lock-in and pull-in ranges, known from engineering literature. The comparison shows that those lock-in and pull-in range estimates may lead to cycle slipping and the loss of synchronization, respectively.

In the present work, a second-order type-2 phase-locked loop (PLL) with a piecewise-linear phase detector characteristic is analyzed. An exact solution to the Gardner problem on the lockin range is obtained for the considered model. The solution is based on a study of cycle slipping bifurcation, which improves the well-known engineering estimates.

In 1981, famous engineer William F. Egan conjectured that a higher-order type 2 PLL with an infinite hold-in range also has an infinite pull-in range, and supported his conjecture with some third-order PLL implementations. Although it is known that for the second-order type 2 PLLs the hold-in range and the pull-in range are both infinite, this brief shows that the Egan conjecture is not valid in general. We provide an implementation of the third-order type 2 PLL, which has an infinite hold-in range and experiences stable oscillations. This implementation and the Egan conjecture naturally pose a problem, which we will call the Egan problem: to determine a class of type 2 PLLs for which an infinite hold-in range implies an infinite pullin range. Using the direct Lyapunov method for the cylindrical phase space we suggest a sufficient condition of the pull-in range infiniteness, which provides a solution to the Egan problem.

Methods of nonlinear analysis and synthesis of synchronization control systems for electrical grids have been developed. The use of averaging methods and Lyapunov-type stability criteria for the cylindrical phase space have made it possible for the first time in the Gardner problem to obtain analytical estimates of the system parameters to ensure acceptable values of phase errors and to take into account changes in the reference signal amplitude.

This paper presents a referenceless baudrate clock and data recovery (CDR) incorporated with a continuous-time linear equalizer (CTLE) and one-tap decision feedback equalizer (DFE) to achieve data rates from 22.5 to 32 Gb/s across a channel with Nyquist loss ranging from 10.1 to 14.8 dB. The referenceless CDR includes a proposed frequency acquisition scheme that consists of two parts: frequency detection and frequency correction. Frequency detection is achieved by examining rising and falling data waveforms to detect discrepancies between the data rate and the locally recovered clock frequency. Frequency correction uses digitally adjustable asymmetry of the proposed adjustable baud-rate phase detector to correct any frequency error. The receiver is implemented in the TSMC 28-nm CMOS process with an analog front end consisting of a CTLE, sampling comparators, a digitally controlled oscillator, and a digital back end consisting of synthesized digital CDR logic. The open-loop frequency detector range is measured to be 39%. The closed-loop CDR capture range is measured to be 34%, limited by test equipment. The proposed frequency acquisition scheme improves the measured CDR capture range by up to 227×. At 32 Gb/s, the entire receiver consumes 102.04 mW, achieving energy consumption below 3.19 pJ/b.

A highly digital two-stage fractional-N PLL architecture utilizing a first order 1-bit frequency-to-digital converter (FDC) is proposed and implemented in 65 nm CMOS process. Performance of the first order 1-bit FDC is improved by using a phase interpolator (PI) based fractional divider that reduces phase quantizer input span and by using a multiplying delay-locked loop (MDLL) that increases its oversampling ratio. We also describe an analogy between a time-to-digital converter (TDC) and a FDC followed by an accumulator that allows us to leverage the TDC-based PLL analysis techniques to study impact of FDC characteristics on FDC-based fractional-N PLL (FDCPLL) performance. Utilizing proposed techniques, a prototype PLL achieves 1 MHz bandwidth, -101.6 dBc/Hz in-band phase noise, and 1.22 ps rms (1 kHz-40 MHz) jitter while generating 5.031 GHz output from 31.25 MHz reference clock input. For the same output frequency, the stand-alone second-stage fractional-N FDCPLL achieves 1 MHz bandwidth, -106.1 dBc/Hz in-band phase noise and 403 fs rms jitter with a 500 MHz reference clock input. The two-stage PLL consumes 10.1 mW power from a 1 V supply, out of which 7.1 mW is consumed by the second-stage FDCPLL.

Phase-shifting is one of the most useful methods of phase recovery in digital interferometry in the estimation of small displacements, but miscalibration errors of the phase shifters are very common. In practice, the main problem associated with such errors is related to the response of the phase shifter devices, since they are dependent on mechanical and/or electrical parts. In this work, a novel technique to detect and measure calibration errors in phase-shifting interferometry, when an unexpected phase shift arises, is proposed. The described method uses the Radon transform, first as an automatic-calibrating technique, and then as a profile measuring procedure when analyzing a specific zone of an interferogram. After, once maximum and minimum value parameters have been registered, these can be used to measure calibration errors. Synthetic and real interferograms are included in the testing, which has thrown good approximations for both cases, notwithstanding the interferogram fringe distribution or its phase-shifting steps. Tests have shown that this algorithm is able to measure the deviations of the steps in phase-shifting interferometry. The developed algorithm can also be used as an alternative in the calibration of phase shifter devices.

This article presents an amplitude and 360º phase shift array measurement system. The basic cell of the measurement system uses a novel amplitude and phase detector based on switched dual multipliers. The phase shift measurement is characterized using an analog phase detector (mixer), detecting a maximum range of ±90º, and a double multiplication of the input signals, in phase and phase shifted. This method broadens the frequency and amplitude range beyond other solutions that require fulfilling the quadrature condition. This method broadens the frequency and amplitude beyond other solutions requiring fulfilling the quadrature condition or phase and amplitude balance. Thus, it enables to compensate significant phase imbalance in the 90º hybrid or use amplitudes out of the range that ensures the switching operation of mixer diodes. The circuit calibration that allows compensation for errors (amplitude, phase shift,
mismatching, etc.) is detailed, and its relation to the required measurement accuracy is discussed. The design can be easily extrapolated to other frequency ranges because it uses commercial RF devices available in a wide frequency range and avoids the need of crossing lines or complex 90º hybrid. A prototype with 3x3 cells has been built to evaluate various test conditions on 1x3 cell configurations that show the advantages of the
procedure. It should be highlighted that the cell prototype uses devices that will be operating outside the frequency and amplitude ranges recommended by their manufacturers. A calibration from 2.6 to 6 GHz and -15 to -3 dBm was performed to evaluate the measurement errors. An analysis of the isolation between cells and different calibration configurations is performed to analyze the measurement errors. Measurements show compensation of +30º /-25º phase imbalance and 13 dB power lower than mixer manufacturer recommendation

The Cole-impedance model is extensively utilized for modelling the electrical impedance of biological samples, including agricultural goods (e.g. fruits and vegetables). The conventional methods for estimating parameters of the Cole-impedance model rely on processing multi-frequency impedance datasets using non-linear least squares methods. The quality of the initial value used in these methods has a direct impact on the convergence and estimation accuracy, while requirement for complex processing units lowers portability and in-situ applications. This paper introduces method not dependent on a particular platform to estimate parameters of the Cole-impedance model that best represent an impedance dataset, eliminating the need for the specific toolbox within the software package, and it does not necessitate the user to supply initial values. The proposed method is validated using synthetic datasets (with and without noise) and experimental bioimpedance of carrot, potato, and pear samples. Further, it is implemented on a low-cost embedded hardware with execution time <7 seconds (for an impedance dataset with 256 datapoints) and estimation accuracy comparable to PC-based estimations. The embedded hardware is interfaced wirelessly to a smartphone application to demonstrate the in-situ graphical evaluation and reporting available using the proposed system.

This thesis presents the theory and analysis of IF polar receiver (PRX) architecture. By using new quantization techniques in the polar domain, the proposed receiver can boost the signal to quantization noise ratio (SQNR) compared to a traditional rectangular (I/Q) receiver. The proposed PRX is composed of a magnitude and a phase quantizer. The magnitude quantizer is similar to the conventional rectangular quantizer in voltage domain. The phase quantizer employs a time-todigital converter (TDC) for phase detection. Furthermore, an intuitive graphical method is used to analyze the quantization properties of the polar quantization. A 10 bit polar quantizer is designed and fabricated in 130nm CMOS, and achieves 2-to 5-dB of SQNR improvement compared to rectangular quantizer for signal bandwidths as high as 20MHz.

Renewable energy sources like wind, sun, and hydro are seen as a reliable alternative to the traditional energy sources such as oil, natural gas, or coal. Distributed power generation systems (DPGSs) based on renewable energy sources experience a large development worldwide. Due to the increasing number of DPGSs connected to the utility network, new and stricter standards in respect to power quality, safe running and islanding protection are issued. This paper analyzed the operation of synchronization grid connected VSI with the grid using SVPWM method. The paper also gives an overview of synchronization methods and a discussion about their importance in the control.

Zero crossing detection is the most common method for measuring the frequency or the period of a periodic signal. This paper presents a comparative study of various zero crossing detector techniques. The accuracy of measuring zero crossing for synchronizing power system control and instrumentation requires a diverse approach to minimize phase detection errors from signals corrupted with noise and extraneous signals. An approach to detect zero crossing with the use of opto coupler is detailed describe in the paper. The issues related to the previous approaches has been discussed along with their pros and cons.

Ce travail est le fruit d'un long parcours et de multiples influences auxquelles je ne saurais rendre pleinement justice. Je voudrais évoquer d'abord avec reconnaissance la mémoire de Jean-Jacques Origas, dont l'influence fut décisive dans ma formation à l'Institut national des langues et civilisations orientales. Je voudrais exprimer ma reconnaissance aux nombreux acteurs qui ont bien voulu jouer le rôle d'informants, des auteurs d'articles aux utilisateurs de logiciels, ainsi qu'aux étudiants sagaces et aux collaborateurs qui m'ont posé des questions judicieuses. Les personnes qui ont échangé leurs connaissances au cours des années sont nombreuses et je voudrais leur témoigner ma gratitude ; pour leurs discussions fructueuses dans le domaine de la linguistique japonaise, en particulier Catherine Garnier à l'INALCO, puis à l'EHESS, Irène Tamba,

The detector uses phase compensation for detecting sinusoidal signal with unknown amplitude, frequency, and phase in complex Gaussian noise with unknown variance. We analyze the statistical properties of the discrete Fourier transform (DFT) of the observations and consider the leakage effect. Then we develop the detector by using generalized likelihood ratio test (GLRT). The new detector fully utilizes the phase information of the signal and achieves constant false alarm rate (CFAR) property. Theoretical analysis and simulation results show its improvement in detection performance.

This paper presents a new circuit for clock generation. A new phase frequency detector is designed in 130nm CMOS process technology. The phase locked loop is designed to meet the 10BaseKR wire line communication standards. All the circuits are designed in current mode logic for high speed operation. The designed circuit dissipates mW. The voltage controlled oscillator has phase noise of -182.2dBc/Hz at 1 MHz offset from center frequency. The designed phase locked loop has rms phase jitter of 44.17fs.

Electron impact excitation of lithium (2s-3s) and sodium (3s-4s) atoms in the presence of a resonant laser field is studied. The frequency of the laser field is chosen to match the 2s-2p (3s-3p) transition frequency in the lithium (sodium) atom. The variation of the total cross section with laser intensity and incident energy is presented.

The performance of a downlink synchronous MC-CDMA system with joint frequency-time domain spreading (MC-2D-CDMA) is investigated in this paper. We propose a two dimensional adaptive minimum mean square error (MMSE) receiver, which works in decision-directed mode after an initial training period. A subcarrier phase tracker, which comprises a bank of phase locked-loops (PLLs), is employed in the receiver to track the fading phase variability. Furthermore, a simplified phase tracker structure is proposed to reduce the system complexity. The performance of the data detector and the behavior of the phase tracker are analyzed theorectically in this paper and are shown to match the simulation results. Both analysis and simulation indicate that the proposed system outperforms the conventional MC-DS-CDMA systems by exploiting frequency diversity and facilitating subcarrier synchronization.

A fast lock DLL based 800Mb/s to 3.2 Gb/s burst mode memory interface is implemented. The DLL employs a two-step TDC during power up from 0mW to lock within 3 cycles with residual error < 33 mUI. Following initial lock, the DLL operates closed-loop to compensate for V,T drift consuming 6mW @ 1.6GHz. In addition the DLL filters high frequency input jitter and corrects 20% DCD without additional correction.

the need of adding parasitic patches in another layer or in the same layer. It is thus a single-layer single-patch wideband microstrip antenna. The widehand behaviour is probably due to the fact that the currents along the edges of the slot introduce an additional resonance, which, in conjunction with the resonance of the main patch, produce an overall broadband frequency response characteristic. The slot also appears to introduce a capacitive reactance which counteracts the inductive reactance of the probe. However, the exact mechanism responsible for the wideband behaviour is not well understood at the present time. Much experimental and theoretical study is needed to characterise this antenna. Such studies are currently in progress.

The application of conventional antenna phase measurement methods becomes increasingly difficult above 100 GHz. The main problems are the complexity of measurement set-ups and errors caused by the flexible cables or rotary joints needed in the system. To overcome these problems, a novel differential phase measurement method has been developed and used to measure phase centre positions and phase patterns of two corrugated horns at 105-115 GHz and 176-190 GHz. In spite of the simplicity, the differential phase method gives accurate results. Good agreement between the measured values and theoretical values, calculated with the modal matching technique, were obtained.

This paper presents an all-digital half-rate referenceless CDR with a single direction frequency acquisition achieved. Thanks to asymmetric binary phase detector (ABPD), compared with existed inverse alexander phase detector (IAPD), we changed the input-output characteristic to enable accumulated phase error point in the same direction when frequency error happens while the output of IAPD has no directivity. Once the frequency of the digital controlled oscillator (DCO) enters the pull-in range of the CDR loop, the phase is automatically locked. To improve jitter tolerance (JTOL) performance further, IAPD logic is enabled, and ABPD is disabled after locking. The prototype was implemented in a 28 nm low power CMOS process with a data rate tracking range of 9-11 Gb/s. The measured JTOL is 0.35 UI at high frequency with PRBS31 input data pattern.

A time signal distribution system is an important part of several engineering assemblies being present in process controlling equipment, distributed computation systems and telecommunication networks. In order to have accurate performance, synchronous operation of these systems, composed by several nodes, needs a reliable time basis signal extracted from the line data stream in each node. When the nodes are synchronized, routing and detection can be performed, guaranteeing the correct sequence of information distribution among the several users of a shared circuit. Consequently, an auxiliary network is created inside the main circuit, a sub-network, dedicated to the distribution of the clock signals. There are different solutions for the architecture of the time distribution sub-network and choosing one of them depends on cost, precision, reliability and operational security. In this work an overview of the possible time distribution schemes is given. Additionally, a detailed study of a robust option is presented by using the qualitative theory of differential equations. Correspondences between constitutive parameters of the network and the dynamics of the spatial phase and frequency errors are established.

A model of motion detection is presented. The model contains three stages. The first stage is unoriented and is selective for contrast polarities. The next two stages work in parallel. A phase insensitive stage pools across different contrast polarities through a spatiotemporal filter ...

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Previous study showed that a third-order phase-locked loop (PLL) with sinusoidal phase detector characteristics experienced a Hopf bifurcation point as well as chaotic behavior. As a result, this behavior drives the PLL to the out-oflock (unstable) state. The analysis was based on a modern nonlinear theory such as bifurcation and chaos. The main goal of this paper is to control this chaotic behavior. A nonlinear controller based on the theory of backstepping is designed. The study showed the effectiveness of the designed nonlinear controller in controlling the undesirable unstable behavior and pulling the PLL back to the in-lock state.

In this paper we have designed and implemented two all-digital phase-locked loop models one with an XOR gate as phase detector and the other with edge triggered JK flip flop as Phase Detector. The proposed models are implemented by using Very High Speed Integrated Circuit Hardware Description Language. The simulation has been performed in ISE Xilinx 14.2 software platform to study the power consumptions and synthesis characteristics of the models. The power consumptions of the models are evaluated from Xilinx Power Estimator. It is observed that the power consumption of the model with XOR gate and with edge triggered JK FF phase detector are recorded to be 15 mW and 21 mW respectively at ambient temperature of 25° C.

To demodulate the input signal, the receiver must align its local radio frequency oscillator with the frequency and phase of the received signal's unmodulated carrier as well as align its sampling clock with the epochs of the underlying modulation process embedded in the received signal. When the frequency offset of the received signal is quite small phase locked loop (PLL) can be used to drive the phase error to zero, however PLLs fail to operate when the received signal has a significant frequency offset. Thus, when a significant frequency offset does exist, it must be estimated and removed prior to the PLL. Frequency locked loop (FLL) are used to accomplish this task. The maximum likelihood frequency estimator uses a frequency detector formed by a pair of band edge (BE) filters. Oddly, there is remarkably little information in the literature on the ability of the band edge filter to support the modulation timing acquisition. In this paper we show how the band edge filter can support two synchronization tasks of carrier frequency acquisition and modulation timing acquisition. We present a receiver architecture and demonstrate its ability to acquire carrier frequency and timing phase alignment without data aided observations.

In this paper, a novel fast phase detection system for all-digital phase locked loop (ADPLL) is presented. The phase detection system is realized by generating an analytic signal using a compact implementation of Hilbert transform and then simply computing the instantaneous phase. 16-bit CORDIC algorithm is employed in order to obtain the phase information of the signal. All the components used in this phase detector system are realized as digital discrete time components. This design does not involve any class of multipliers thus reducing the complexity of the design. The phase detection system although providing a definite advantage over conventional analog phase detectors, The Hilbert filter implemented in this paper has been designed using a method based on complex, multiplier less sampling filters. A comparison has been drawn between the continuous PLL model's phase detection system and the proposed method for effectiveness of the study. The studied system is modeled and tested in the MATLAB/Simulink environment.

The use of optical clocks/oscillators in future ultra-precise navigation, gravitational sensing, coherent arrays, and relativity experiments will require time comparison and synchronization over terrestrial or satellite free-space links. Here we demonstrate full unambiguous synchronization of two optical timescales across a free-space link. The time deviation between synchronized timescales is below 1 fs over durations from 0.1 s to 6500 s, despite atmospheric turbulence and kilometer-scale path length variations. Over several days, the time wander is 40 fs peak-to-peak. Our approach relies on the two-way reciprocity of a singlespatial-mode optical link, valid to below 225 attoseconds across a turbulent 4-km path. This femtosecond level of time-frequency transfer should enable optical networks using state-of-the-art optical clocks/oscillators.

This work demonstrates the ability of the Ion-Sensitive Field-Effect Transistor (ISFET)-based immunosensor to detect antibodies against the human leukocyte antigen (HLA) and the major histocompatibility complex class-I-related chain A (MICA). The sensing membrane of the ISFET devices was modified and functionalized using an APTES-GA strategy. Surface properties, including wettability, surface thickness, and surface topology, were assessed in each module of the modification process. The optimal concentrations of HLA and MICA proteins for the immobilization were 10 and 50 μg/mL. The dose-response curve showed a detection range of 1.98–40 µg/mL for anti-HLA and 5.17–40 µg/mL for anti-MICA. The analytical precision (%CV) was found to be 10.69% and 8.92% for anti-HLA and -MICA, respectively. Moreover, the electrical signal obtained from the irrelevant antibody was considerably different from that of the specific antibodies, indicating the specific binding of the relevant antibodies witho...