Network Processor

Network verification to detect router configuration errors typically requires an explicit correctness specification. Unfortunately, specifications often either do not exist, are incomplete, or are written informally in English. We describe an approach to infer likely network configuration errors without a specification through a form of automated outlier detection. Unlike prior techniques, our approach can identify outliers even for complex, structured configuration elements that have a variety of intentional differences across nodes, like accesscontrol lists, prefix lists, and route policies. Given a collection of configuration elements, our algorithm automatically infers a set of parameterized templates, modeling the (likely) intentional differences as variations within a template while modeling the (likely) erroneous differences as variations across templates. We have implemented our algorithm, which we call structured generalization, in a tool called SELFSTARTER and used it to automatically identify configuration outliers in a collection of datacenter networks from a large cloud provider, the wide-area network from the same cloud provider, and the campus network of a large university. SELFSTARTER found misconfigurations in all three networks, including 43 previously unknown bugs, and is in the process of adoption in the configuration management system of a major cloud provider.

Network verification to detect router configuration errors typically requires an explicit correctness specification. Unfortunately, specifications often either do not exist, are incomplete, or are written informally in English. We describe an approach to infer likely network configuration errors without a specification through a form of automated outlier detection. Unlike prior techniques, our approach can identify outliers even for complex, structured configuration elements that have a variety of intentional differences across nodes, like accesscontrol lists, prefix lists, and route policies. Given a collection of configuration elements, our algorithm automatically infers a set of parameterized templates, modeling the (likely) intentional differences as variations within a template while modeling the (likely) erroneous differences as variations across templates. We have implemented our algorithm, which we call structured generalization, in a tool called SELFSTARTER and used it to a...

with the growth of Internet traffic and using Gb/s or 10 Gb/s links in backbone, the speed of forwarding packets in intermediate devices is crucial. Routers must be able to forward millions of packets per second on each of their interfaces. Finding a method that can speed up the IP lookup is one of the challenges in network research. There are two approaches to implement IP lookup, hardware-based and software-based. For software-based approach many algorithms have been proposed based on the tries concept. Some parallel algorithms have been suggested to exploit routers equipped with multi-core CPUs. In this paper, we propose a new approach that was constructed by combining the useful characteristics of the Priority trie and parallel processing. Our method consists of a trie and several subtries based on prefix length. These subtries processed by a specific thread to speed up IP lookup functionality. This proposed data structure inherits simplicity of Priority tries. Simulation results illustrate that our method speeds up IP lookup processing although memory usage has not been increased.

Regular expressions provide a flexible means for matching strings and they are often used in dataintensive applications. They are formally equivalent to either deterministic finite automata (DFAs) or nondeterministic finite automata (NFAs). Both DFAs and NFAs are affected by two problems known as amnesia and acalculia, and DFAs are also affected by a problem known as insomnia. Existing techniques require an automata conversion and compaction step that prevents the use of existing automaton databases and hinders the maintenance of the resulting compact automata. In this paper, we propose Parallel Finite State Machines (PFSMs), which are able to run any DFAor NFA-like state machines without a previous conversion or compaction step. PFSMs report, online, all the matches found within an input string and they solve the three aforementioned problems. Parallel Finite State Machines require quadratic time and linear memory and they are distributable. Parallel Finite State Machines make very fast distributed regular expression matching in data-intensive applications feasible.

The battle between traffic demand and resource availability limits the efficiency of the existing cellular network. To overcome these limitations, the 5G needs to be scalable and flexible to allow multiple radio access technology. The next-generation base station architecture also aims to maximize physical resource utilization and minimize its associated cost. In this paper, we proposed a framework for inter-BBU load balancing based on VB's live migration in a C-RAN architecture. The migration is performed in-between two C-BBU, which resides at a single BBU-Pool. The load balancing across BBU is performed based on two consecutive steps, i.e. (a) an expected completion time-based resources allocation and (b) a utilization factor-based VB migration. We validate our proposed approach using 𝐶𝑙𝑜𝑢𝑑𝑆𝑖𝑚 simulator. The result shows that the adaptation of cloudcomputing technology along with suitable resources allocation and load balancing strategy increases BBU utilization by overcoming the imbalance load conditions. Further, the use of the live migration technique improves the QoS of C-RAN by reducing the server downtime and migration time.

In this paper we present result f rom an app lication integrated congestion control mechanism designed for time-sensitive traffic based on the principle of direct protocol i nteractivity. In contrast t o classical t ransport protocols we e nvision a transport mechanism, which is interactive and can p rovide event notification to the subscriber of it s communication service. We then show a friendly adaptive MPEG-2 video transcoding scheme, which d irectly interacts with the transport protocol and adjusts its production in synch with the impairment events in the transport l ayer. In this paper we present t he application side symbiotic mechanics, and report potential dramatic improvement i n time-bounded video delivery. The system can be implemented with relative simple and direct modification o f t he c urrent TCP transport.

Applications requiring high-speed TCP/IP processing can easily saturate a modern server. We and others have previously suggested alleviating this problem in multiprocessor environments by dedicating a subset of the processors to perform network packet processing. The remaining processors perform only application computation, thus eliminating contention between these functions for processor resources. Applications interact with packet processing engines (PPEs) using an asynchronous I/O (AIO) programming interface which bypasses the operating system. A key attraction of this overall approach is that it exploits the architectural trend toward greater thread-level parallelism in future systems based on multi-core processors. In this paper, we conduct a detailed experimental performance analysis comparing this approach to a best-practice configured Linux baseline system.We have built a prototype system implementing this architecture, ETA+AIO (Embedded Transport Acceleration with Asynchro...

The ETA project at Intel Research and Development has developed a software prototype that uses one of the Intel® Xeon TM processors in a multi-processor server as a packet processing engine. The prototype is used as a vehicle for empirical measurement and analysis of a highly programmable packet processing engine that is closely tied to the server's core CPU and memory complex. The usage model for the prototype is the acceleration of server TCP/IP networking. The ETA prototype runs in an asymmetric multiprocessing mode, in that the packet processing engine does not run as a general computing resource for the host operating system. We show an effective method of interfacing the packet processing engine to the host processors using efficient asynchronous queuing mechanisms. This paper describes the ETA software architecture, the ETA prototype, and details the measurement and analysis that has been performed to date. Test results include running the packet processing engine in singlethreaded mode, as well as in multi-threaded mode using Intel's Hyper-Threading Technology (HT). Performance data gathered for network throughput and host CPU utilization show a significant improvement when compared to the standard TCP/IP networking stack.

Abstract—Multiple core processors have already became the dominant design for general purpose CPUs. Incarnations of this technology are present in solutions dedicated to such areas like computer graphics, signal processing and also computer networking. Since the ...

Contemporary data centers implement hybrid storage systems that consist of layers from solid-state drives (SSDs) and hard disk drives (HDDs). Due to their high data retrieval speed, SSDs layer is used to store important data blocks that have features like high frequency of access. To boost their security level, many of such systems implement self-encryption algorithms like advanced encryption standard (AES), Blowfish, and triple data encryption standard (3DES) with different key sizes that vary in their complexity and their decryption latency whenever a block is requested for read. Frequently accessed data blocks with increased decryption latencies are better to be migrated to the SSDs layer to decrease their retrieval latency. In this paper, we introduce a linear complexity algorithm hybrid self-encryption storage data migration (HSESM) that migrates important data blocks that requires long decryption latencies from the HDDs layer to the SSDs one. Performance evaluation shows that HSESM data migration process can reduce data blocks read latencies in 13.71%-23.61% under worst-case scenarios.

The High-Level Architecture (HLA) standard developed by the Department of Defense in the United States is a key technology to perform distributed simulation. Inside the HLA framework, many different simulators (termed federates) may be interconnected to create a single more complex simulator (federation). Data Distribution Management (DDM) is an optional subset of services that controls which federates should receive notification of state modifications made by other federates. A simple DDM implementation will usually generate much more traffic than needed, whereas a complex one might introduce too much overhead. In this work, we describe an approach to DDM that delegates a portion of the DDM computation to a processor on the network card in order to provide more CPU time for other federate and Runtime Infrastructure (RTI) computations while still being able to exploit the benefits of a complex DDM implementation to reduce the amount of information exchange.

Efficient management of concurrent access to shared resources is crucial in modern multi-threaded systems to avoid race conditions and performance bottlenecks. Traditional locking mechanisms, such as standard read-write locks, often introduce substantial overhead in read-heavy workloads due to their blocking nature. To address these challenges, we introduce the LRW lock: lightweight read-write lock. It allows concurrent read access and ensures exclusive write access. The lock considers atomic operations to provide active readers and writers. This paper, initially presents algorithms to acquire read and write locks using a locking object of the LRW lock. Later, it provides the design of non-blocking methods tryReadLock() and tryWriteLock() for read and write operations. The methods offer flexibility for timesensitive applications. To understand the efficiency of the LRW lock, we consider different concurrent data structures and the state-of-the-art locking object. Experimental results show that the implementation that considers LRW lock outperforms the state-of-the-art locking object and consumes less memory footprint. The LRW lock leverages atomic operations to track active readers and writers efficiently.

Managing peer-to-peer traffic is a major challenge for network administrators, because peer-to-peer applications tend to use dynamic port numbers and proprietary protocols. In view of this problem, we propose an approach that combines the advantages of payload-based and transport-layer approaches, and avoids their disadvantages. Specifically, our approach can recognize particular peer-to-peer applications running on the monitored host without checking packet payloads. The experiment results show that our scheme can successfully recognize the traffic from BitTorrent, eMule, or Skype with 98% correct rate within 6 minutes and 99% correct rate within 15 minutes.

Software-based network packet processing on standard high volume servers promises better flexibility, manageability and scalability, thus gaining tremendous momentum in recent years. Numerous research efforts have focused on boosting packet processing performance by offloading to discrete graphics processing units (GPUs). While integrated GPUs, residing on the same die with the CPU, offer many advanced features such as on-chip interconnect CPU-GPU communication, and shared physical/virtual memory, their applicability for packet processing workloads has not been fully understood and exploited. In this paper, we conduct in-depth profiling and analysis to understand the integrated GPU's capabilities, and performance potential for packet processing workloads. Based on that understanding, we introduce a GPU accelerated network packet processing framework that fully utilizes integrated GPU's massive parallel processing capability without the need for large numbers of packet batching, which might cause a significant processing delay. We implemented the proposed framework and evaluated the performance with several common, light-weight packet processing workloads on the Intel R Xeon R Processor E3-1200 v4 product family (codename Broadwell) with an integrated GT3e GPU. The results show that our GPU accelerated packet processing framework improved the throughput performance by 2-2.5x, compared to optimized CPU-only for packet processing.

Software-based network packet processing on standard high volume servers promises better flexibility, manageability and scalability, thus gaining tremendous momentum in recent years. Numerous research efforts have focused on boosting packet processing performance by offloading to discrete graphics processing units (GPUs). While integrated GPUs, residing on the same die with the CPU, offer many advanced features such as on-chip interconnect CPU-GPU communication, and shared physical/virtual memory, their applicability for packet processing workloads has not been fully understood and exploited. In this paper, we conduct in-depth profiling and analysis to understand the integrated GPU's capabilities, and performance potential for packet processing workloads. Based on that understanding, we introduce a GPU accelerated network packet processing framework that fully utilizes integrated GPU's massive parallel processing capability without the need for large numbers of packet batching, which might cause a significant processing delay. We implemented the proposed framework and evaluated the performance with several common, light-weight packet processing workloads on the Intel R Xeon R Processor E3-1200 v4 product family (codename Broadwell) with an integrated GT3e GPU. The results show that our GPU accelerated packet processing framework improved the throughput performance by 2-2.5x, compared to optimized CPU-only for packet processing.

In this paper, we present a relatively primitive execution model for fine-grain parallelism, in which all synchronization, scheduling, and storage management is explicit and under compiler control. This is defined by a threaded abstract machine (TAM) with a multilevel scheduling hierarchy. Considerable temporal locality of logically related threads is demonstrated, providing an avenue for effective register use under quasidynamic scheduling. A prototype TAM instruction set, TLO, has been developed, along with a translator to a variety of existing sequential and parallel machines. Compilation of Id, an extended functional language requiring fine-grain synchronization, under this model yields performance approaching that of conventional languages on current uniprocessors. Measurements suggest that the net cost of synchronization on conventional multiprocessors can be reduced to within a small factor of that on machines with elaborate hardware support, such aa proposed dataflow architectures. This brings into question whether tolerance to latency and inexpensive synchronization require specific hardware support or merely an appropriate compilation strategy and program representation.

The Ethernet speed has increased sending and receiving frames from 40 to 100 Gbps after the IEEE P802.3ba released. The industry and academia have focused scaling up the TCP/IP protocol processing for 40-100 Gbps. LSO is a de facto standard, which is offloaded to network interface for sending packets up to 10 Gbps. It not clears whether a network interface can support such function for new 40-100 Gbps. The widely use of the hardware-based NIC such as the use of a fully customized logic based network interface can be due to the following reasons; Still it is not clear whether the General Purpose Processor (GPP) can provide the processing required for high-speed line beyond the 10 Gbps. Also, the limit of the GPP's clock in supporting the processing of network interfaces. However, using a RISC core engine for offloading the LSO function can deliver some important features to network interfaces design, such as simplicity, scalability, shorter developing cycle time. In this paper, we have investigated using a specialized RISC core to process the LSO functions for TCP/IP and UDP/IP for highspeed communications rate up to 100 Gbps. To achieve this, we have enhanced the LSO algorithm to scale it to 100 Gbps. A fast DMA is used to support transferring data in the network interface. The LSO processing methodology on the network has presented. In addition, the RISC's performance and data movements for high communication rate up to 100 Gbps have been measured. A 148 MHz RISC core can support the sendingside processing for up to 100 Gbps transmission speed for the TCP/IP and UDP/IP protocol when the MTU is applied (1500 bytes). A DMA with 3759 MHz is required to eliminate the idle cycles while transferring data over the 64-bit local bus.

Today major challenges are faced by server platforms while processing TCP/IP or UDP/IP. For instance, the speed of networks now exceeds the gigabit per sec Gbps, the design and implementations of high-performance Network Interfaces (NI) have become very challenging. There are different possible design approaches to implement high-speed NI. However, using the General Purpose Processor (GPP) as a core engine to offload some, if not all, of the TCP/IP or UDP/IP protocol functions can deliver some important features to NIs, such as simplicity, scalability, shorter development cycle time and reduced costs. Still it is not clear whether the GPP can provide the processing required Ethernet beyond 10 Gbps. Also, what is the limit of such GPP in supporting the processing of network interfaces? In this paper, we have measured the amount of processing required for Ethernet Network Interfaces (ENI) supporting different transmission line speeds. A NI-programmable based RISC model has been designed to measure the processing required for the ENI. The results have shown that a RISC core running at 240 MHz can be used as a processing core in high-speed ENI. Such core can support a wide range of transmission line speeds, up to 100 Gbps. Also, we have discussed some of the design issues that are related to RISC core based NI and the data movement type.

The design of a new high-performance computing platform to model biological neural networks requires scalable, layered communications in both hardware and software. SpiNNaker's hardware is based upon Multi-Processor System-on-Chips (MPSoCs) with flexible, power-efficient, custom communication between processors and chips. The architecture scales from a single 18-processor chip to over 1 million processors and to simulations of billion-neuron, trillion-synapse models, with tens of trillions of neural spike-event packets conveyed each second. The communication networks and overlying protocols are key to the successful operation of the SpiNNaker architecture, designed together to maximise performance and minimise the power demands of the platform. SpiNNaker is a work in progress, having recently reached a major milestone with the delivery of the first MPSoCs. This paper presents the architectural justification, which is now supported by preliminary measured results of silicon performance, indicating that it is indeed scalable to a million-plus processor system.

Modern Network Intrusion Detection Systems (NIDS) inspect the network packet payload to check if it conforms to the security policies of the given network. This process, of-ten referred to as deep packet inspection, involves detection of predefined signature strings or keywords starting at an arbitrary location in the payload. String matching is a computationally intensive task and can become a potential bottleneck without high-speed processing. Since the conventional software-implemented string matching algorithms have not kept pace with the increasing network speeds, special purpose hardware solutions have been introduced. In this paper we show how Bloom filters can be used effectively to perform string matching for thousands of strings at wire speed. We describe how Bloom filters can be implemented feasibly on commodity FPGA. Our analysis shows that this approach for string matching is more effective than the current FPGA-based solutions which use Deterministic or Non-deterministic Finite Automata (DFA or NFA). Fi-nally, we give the details of our implementation of string matching technique on Xilinx XCV 2000E FPGA.

With significant advances in network interfaces, I/O bus, and processor architecture of end node, innovative approaches are required to achieve high network bandwidth by fully utilizing available system resources. The issues related can be summarized into two: i) Utilizing I/O bus bandwidth for high bandwidth network connection and ii) Utilizing multiple cores for high packet processing throughput. In this paper, we conduct several experiments on a multi-core system with 10GigE and multi-port 1GigE network interfaces. We aim to show the impact of system configurations on the network performance and compare the performance of two different network interfaces. The experimental results show that, with the proper interrupt affinity configurations, the multi-port 1GigE can achieve comparable bandwidth to 10GigE. The peak bandwidth achieved by the multi-port 1GigE is 6.7Gbps, which is more than 80% of the theoretical maximum I/O bus bandwidth on the experimental system. We, however, also show that the multi-port 1GigE can consume much more processor resource than 10GigE. More importantly, we reveal that processing the packets on many cores can result in more resource consumption without much benefit. This can be because of locking overhead between softirqs running on different cores and lower cache efficiency. We show that the more tuning on the configuration cannot overcome this side effect.

The design of high performance application-specific processors is the bottleneck in many applications. In critical high data rate network devices such as modems and other end-user interfaces, the packet forwarding engine requires both high degree o.fflexibility (to support large number of protocols) as well as extremely high performance (to be able to support Gigabit processing). While hardware application-specific designs can cope with performance, they lack flexibility. Although software based solutions could be ideal to meet flexibility and low cost constraints, unfortunately, they miss the speed performance requirement. The main goal of this paper is to present an architectural model to design a new processor architecture based on multiple cores and specific dedicated hardware units. In particular, we propose a new model which takes into account networkprotocols characteristics and input traffic nature to meet performance and cost requirements.

Data: 24 de febrer de 2006 Actualment, els serveis òptics són essencialment estàtics, en els que els usuaris sol•liciten als proveïdors o ISPs l'ample de banda que necessiten Durant un cer període de temps. Aquest serveis s'aprovisionen de forma manual, la qual cosa pot suposar un treball llarg i costós. Els usuaris o les mateixes aplicacions necessiten flexibilitat per controlar els seus serveis al llarg de diferents dominis independents, ja que estan en millor posició que els proveïdors per escollir i gestionar camins òptics adaptats a les seves necessitats. Aquesta idea ha donat lloc a un nou paradigma en el mon de les xarxes anomenat "xarxes controlades per usuaris". Amb el patrocini de Canarie, s'està duent a terme una investigació per tal d'aconseguir les xarxes controlades pels usuaris. D'aquesta investigació ha sorgit un sistema anomenat "User-Controlled Lightpath Provisioning" (UCLP) (Provisió de camins òptics controlats per usuaris) que permet als usuaris establir canals òptics d'extrem a extrem a través de diferents Sistemes Autònoms. Aquest software s'està desenvolupant al CRC (Communications Research Centre, Canada) amb la col•laboració de la Fundació i2Cat. UCLP es un sistema de gestió distribuït que utilitza la idea de OON (Objecte Orientat a Xarxa) i que es pot explicar com una eina de partició i configuració que representa cada recurs d'una xarxa física (fibres, targetes) com un servei o objecte. Aquest servei/objecte es pot posar sota el control de diversos usuaris de la xarxa per tal que puguin crear les seves pròpies topologies de xarxa IP. Fins ara, UCLP treballava amb equips de capa 1 i 2. El principal objectiu d'aquest projecte és trobar una solució per integrar equips de capa 3 al sistema. Concretament, es vol introduir un router basat en una nova tecnologia anomenada "estat de flux" (flow-state). Aquesta tecnologia, que permet reconèixer fluxos basats en determinades funcions de hash, realitza un extens procés al primer paquet d'un flux, associa aquest flux amb un estat i aplica el resultat d'aquest procés als següents paquets del flux, amb els quals, enlloc de realitzar enrutament, simplement els reenviarà sense mirar les taules d'enrutament.

In the Internet of things (IoT), network devices and mobile systems should exchange a considerable amount of data with negligible delays. For this purpose, the community has used the software-defined networking (SDN), which has provided high-speed flow-based communication mechanisms. To satisfy the requirements of SDN in the classification of communicated packets, high-throughput packet classification systems are needed. A hardware-based method of Internet packet classification that could be simultaneously high-speed and memory-aware has been proved to be able to fill the gap between the network speed and the processing speed of the systems on the network in traffics higher than 100 Gbps. The current architectures, however, have not been successful in achieving these two goals. This paper proposes the architecture of a processing micro-core for packet classification in high-speed, flow-based network systems. By using the hashing technique, this classifying micro-core fixes the lengt...

Modern network processors employs parallel processing engines (PEs) to keep up with explosive internet packet processing demands. Most network processors further allow processing engines to be organized in a pipelined fashion to enable higher processing throughput and flexibility. In this paper, we present a novel program transformation technique to exploit parallel and pipelined computing power of modern network processors. Our proposed method automatically partitions a sequential packet processing application into coordinated pipelined parallel subtasks which can be naturally mapped to contemporary high-performance network processors. Our transformation technique ensures that packet processing tasks are balanced among pipeline stages and that data transmission between pipeline stages is minimized. We have implemented the proposed transformation method in an auto-partitioning C compiler product for Intel Network Processors. Experimental results show that our method provides impress...

Network Processors (NPs) are emerging as a cost effective network element technology that can he more readily updated and evolved than custom hardware or ASIC-based designs. Moreover, NPs promise support for run-time reconfiguration of low-level networking software. However, it is notoriously difficult to develop software for NPs because of their complex design, architectural heterogeneity, and demanding performance constraints. In this paper we present a runtime componentbased approach to programming NPs. The approach promotes conceptual uniformity and design portability acros a wide variety of NP types while simultaneously exploiting hardware assists that are specific to individual NPs. To show how our approach can be applied in a wide range of types of NPs we characterise the design space of NPs and demonstrate the applicability of our concepts to the various classes identified. Then, as a detailed case study, we focus on programming the Intel IXP1200 NP. This demonstrates that our approach can be effectively applied, e.g. in terms of performance, in a demanding real-world NP environment

Network Processors (NPs) are set to play a key role in the next generation of networking technology. They have the performance of ASIC-based routers whilst offering a high degree of programmability. However, the programmability potential of NPs can only be realised with appropriate software. In this paper we argue that specialised software to support runtime reconfiguration is needed to fully exploit the potential of NPs. We first justify supporting runtime reconfiguration on NPs by offering real-world scenarios and discussing the issues associated with these. We then demonstrate how runtime reconfiguration can be achieved in practice through a case study of our component-based programming approach on the Intel IXP2400 NP.

Some of the costs associated with system virtualization using a virtual machine monitor (VMM) or hypervisor (HV) can be attributed to the need to virtualize peripheral devices and to then manage the virtualized resources for large numbers of guest domains. For higher end, 'smart' IO devices, it is possible to offload selected virtualization functionality onto the devices themselves, thereby creating self-virtualizing devices. A self-virtualizing device is aware of the fact that it is being virtualized. It implements this awareness (1) by presenting to the HV an interface that enables the HV to manage virtual devices on demand, and (2) by presenting to a guest OS a virtual device abstraction that permits it to interact with the device with minimal HV involvement. This paper presents the design of a self-virtualizing network device and its implementation on a modern multi-core network platform, an IXP2400 network processor-based development board. Initial performance results demonstrate that the performance of virtual interfaces is similar to that of regular network interfaces. The longer term goal of this work is to better understand how modern multi-core platforms can be used to realize lightweight , scalable virtualization for future server platforms.

It monitors the network traffic to detect any unwanted attempts to compromise the security of the network by malicious users. Recently an Intrusion Prevention functionality was also added to it. IPS monitors network traffic inline and prevent intrusions by dropping the malicious packets before they reach the actual host. In this thesis, we are adding two functionalities needed to enhance the utility of the system. One of major technique to prevent an IDS/IPS from detecting an attack is through splitting the signature into two packets of a TCP Connection. As the IDS/IPS checks for signature in each packet individually it would not be able to detect this attack. However, on the host machine these packets would be reassembled and a stream of data is available to the application. Hence, it would get compromised. We are adding a TCP Reassembly module to our IPS so that it can detect those attacks which would have went though undetected. We are also adding a Web based Graphical User Inter...

Our work addresses protection of hardware IP at the mask level with the goal of preventing unauthorized manufacturing. The proposed protocol based on chip locking and activation is applicable to a broad category of electronic systems with a primary bus. Such designs include (1) numerous IP offerings for USB, PCI, PCI-E, AMBA and other bus standards typically used in system-on-a-chip designs and computer peripherals, (2) SRAM-based FPGAs that are programmed through an input bus, (3) general-purpose and embedded microprocessors, including soft cores, (4) DSPs, (5) network processors, and (6) game consoles. Our key insight is that such designs can be locked by scrambling the central bus by controlled reversible bit-permutations and substitutions. To securely establish a unique code per chip to control bus scrambling, we employ true random number generators and Diffie-Hellman cryptography during activation.

While general-purpose processors have only recently employed chip multiprocessor (CMP) architectures, network processors (NPs) have used heterogeneous multi-core architectures since the late 1990s. NPs differ qualitatively from workstation and server CMPs in that they replicate many simple, highly efficient processor cores on a chip, rather than a small number of sophisticated superscalar CPUs. In this paper, we compare the performance of one such NP, the Intel IXP 2850, to that of the Intel Pentium 4 when executing a scientific computing workload with a high degree of thread-level parallelism. Our target program, HMMer, is a bioinformatics tool that identifies conserved motifs in protein sequences. HMMer represents motifs as hidden Markov models (HMMs) and spends most of its time executing the well-known Viterbi algorithm to align proteins to these models. Our observations of HMMer on the IXP are therefore relevant to computations in many other domains that rely on the Viterbi algorithm. We show that the IXP achieves a speedup of 1.82 over the Pentium, despite the Pentium's 1.85x faster clock. Moreover, we argue that nextgeneration IXP NPs will likely provide a 10-20x speedup for our workload over the IXP 2850, in contrast to 5-10x speedup expected from a next-generation Pentium-based CMP.

Network management tools must be able to monitor and analyze traffic flowing through network systems. According to the OpenFlow protocol applied in Software-Defined Networking (SDN), packets are classified into flows that are searched in flow tables. Further actions, such as packet forwarding, modification, and redirection to a group table, are made in the flow table with respect to the search results. A novel hardware solution for SDN-enabled packet classification is presented in this paper. The proposed scheme is focused on a label-based search method, achieving high flexibility in memory usage. The implemented hardware architecture provides optimal lookup performance by configuring the search algorithm and by performing fast incremental update as programmed the software controller.

– The paper reports the tests conducted on a dedicated Transducer Independent Interface (TII) to check its compliance with standard IEEE 1451.2 specifications. The interface was built using a synchronous data transfer based on the Serial Peripheral Interface (SPI) protocol ...

Eq hash tables, which support arbitrary objects as keys, distinguish keys via pointer comparison and often employ hash functions that utilize the address of the object. When compacting garbage collectors move garbage collected objects, the addresses of such objects may change, thus invalidating the hash function computation. A common solution is to rehash all of the entries in an eq hash table on the first access to the table after a collection. For a simple stop-and-copy garbage collector, which moves every element of a hash table, the rehashing overhead is proportional to the amount of work done by the collector and so the cost of rehashing adds only constant overhead. Generational copying collectors, however, may move a few or none of the entries, so rehashing a large table may cost considerably more than the garbage collection run that caused the rehash. In other words, such rehashing is not "generation friendly." In this paper, we describe an efficient, generation-friendly mechanism for implementing eq hash tables. The amount of work required for rehashing is proportional to the work performed by the collector as only objects that actually move during a collection are rehashed. The collector supports eq hash tables and their variants via a simple new type of object, a transport link cell, the handling of which by the collector is nearly trivial.

Eq hash tables, which support arbitrary objects as keys, distinguish keys via pointer comparison and often employ hash functions that utilize the address of the object. When compacting garbage collec- tors move garbage collected objects, the addresses of such objects may change, thus invalidating the hash function computation. A common solution is to rehash all of the entries in an eq hash ta- ble on the first access to the table after a collection. For a simple stop-and-copy garbage collector, which moves every element of a hash table, the rehashing overhead is proportional to the amount of work done by the collector and so the cost of rehashing adds only constant overhead. Generational copying collectors, however, may move a few or none of the entries, so rehashing a large table may cost considerably more than the garbage collection run that caused the rehash. In other words, such rehashing is not "genera- tion friendly." In this paper, we describe an efficient, generati...

Increasing on-chip wire delay along with the distributed nature of processing elements, makes instruction scheduling for tiled dataflow architectures very crucial. Our analysis reveals that careful placement of most frequently executed sections of applications, and directly addressing resource contention can significantly improve the performance of the application. The former reduces the operand network latency, while the latter reduces stalls due to contention for processing elements. We augment one of the most recent instruction scheduling algorithms-hierarchical instruction scheduling-to treat loops as a first class entity in placement decisions. In this approach, we avoid splitting the loop between domains, thereby reducing expensive inter-domain traffic by 6.5% and increasing average IPC by 5.13%. In the presence of conditional branches, and variable latency memory instructions, estimating resource contention, at compile time, is not only complex, but also imperfect. We suggest dynamic tracking of contending instructions, and their relocation, once a contention threshold is exceeded. Results showed that dynamic contention tracking reduced the average ALU conflicts by 23%, thereby improving the average IPC by 14.22%. Combined together, these augmentations improve the average IPC by 19.39% and over 30% for some benchmarks.

All rights reserved by www.ijsrd.com 535 FPGA to PC Ethernet Communication using Media Independent Interface (MII) Mode Preeti Kumari Sidharth Kashyap Ajit Jain Lokesh Sharma Department of Electronics Engineering CDAC Noida, GGSIPU Delhi Abstract— As the advancement in the embedded system technology, Field programmable gate array (FPGA) based systems are playing significant role. In many application there is need of high speed communication between FPGA and external world (e.g.-for providing the data of a sensor to the web server in some real time embedded system). In initial phase of development of FPGA Board we had used Universal asynchronous receiver transmitter (UART) for communicating the FPGA to other devices but its speed is too slow in order of thousands of bps. But nowadays modern FPGA board comes with high speed interfaces e.g. Ethernet and PCI Express. We can achieve data rate up to hundreds of Mbps. Ethernet communication provides the required bandwidth for most of the a...

Due to the significant growth of link speeds, amount of data that should be stored on router line cards are rapidly increasing. Therefore, a large number of memory modules are required for packet storage. In addition, a high performance interconnection network on line cards is strongly needed for inter-communication between processing elements and memory modules. In this paper we propose a new interconnection network, known as hyper node torus that can support larger number of nodes compared to other topologies, such as common torus network on a limited area. Simulation results show that hyper node torus can sustain more traffic load, and also it has higher throughput than the torus network under different traffic loads. As a result, it has better scalability and higher performance for using in high-speed packet processors.

This research investigates the feasibility of developing low-cost, personal computer-based parallel processing procedures that can be applicable to real time simulation of freeway flows. Specific objectives include, * Development of a framework for PC-based parallel simulation system * Enhancements of existing freeway traffic models for parallel simulation * Development of a PC-based, parallel simulation algorithm for freeway flows. * Development of a prototype version of a PC-based parallel simulation system Performance evaluation of the PC-based parallel freeway simulation system.

The greatest threats against computer systems around the world come from the cyberspace in the form of cyber-attacks and the zero-day attack is one of such threats faced by computer systems around the world. A vulnerability in system firmware, software, or hardware that is still unknown to the developers or people responsible for it is known as zero-day vulnerability. A zero-day attack is an attack by hackers in which zero-day exploits are applied on a zero-day vulnerability in system firmware, software or hardware before specific security and preventive mechanisms can be identified and set for such vulnerability. This kind of attack is very challenging to defend against because those responsible for the security of such vulnerabilities are unaware of it. Zero-day attacks have been taking a serious upward surge of late and identifying such attacks in real time and quarantining it before it causes more damages to the system is a big problem that computer security personnel are faced with. This research will seek to identify ways in which zero-day attacks can be identified in real time by using a hybrid model that will be proposed. The Signature based defense technique and the Behavior based defense technique are two current security methods that have been identified and this paper will analyze these methods individually and try to find a way in which they can be combined to form a proposed hybrid model.

Cellular Neural Networks (CNN 1) can be embodied in the form of a focal-plane image processor. They represent a computing paradigm with evident advantages in terms of energy and resources. Their operation relies in the strong parallelization of the processing chain thanks to a distributed allocation of computing resources. In this way, image sensing and ultra-fast processing can be embedded in a single chip. This makes them good candidates for portable and/or distributed applications in fields like autonomous robots or smart cities. With the irruption of visual features learning through convolutional neural networks (ConvNets), several works attempt to implement this functionality within the CNN framework. In this paper we carry out some experiments on the implementation of ConvNets with CNN hardware in the form of a focal-plane image processor. It is shown that ultra-fast inference can be implemented, using as an example a LeNetbased ConvNet architecture.

The need for network processors capable of forwarding IP packets at OC-192 and higher data rates has been well established. At the same time, there is a growing need for complex tasks, like packet classification and differentiated services, to be performed by network processors. At OC-768 data rate, a network processor has 9 nanoseconds to process a minimum-size IP packet. Such ultra highspeed processing, involving complex memory-intensive tasks, can only be achieved by multi-CPU distributed memory systems, using very high performance on-chip communication architectures. In this paper, we propose a novel communication network architecture for 8-CPU distributed-memory systems that has the potential to deliver the throughput required in next generation routers. We then show that our communication architecture can easily scale to accommodate much greater number of network nodes. Our network architecture yields higher performance than the traditional bus and crossbar yet has low implementation cost. It is quite flexible and can be implemented in either packet or circuit switched mode. We will compare and contrast our proposed architecture with busses and crossbars using metrics such as throughput and physical layout cost. Recent studies have shown the importance of the on-chip communication architecture used in determining the performance of the overall System-on-Chip (SoC) [4][5][6].