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Key research themes
1. How can test pattern generation and side-channel analysis be optimized to effectively detect hardware Trojans with rare activation conditions?
This research theme focuses on developing test generation methods that improve the likelihood of activating and detecting hardware Trojans (HTs), which are often designed to trigger under very rare internal signal conditions. It emphasizes enhancing side-channel analysis techniques by generating input patterns that maximize switching activity in rare nodes or circuits prone to HT insertion, thereby amplifying power or timing anomalies distinguishable from process variation. This area is crucial because small-sized, stealthy HTs remain dormant under conventional testing, impeding their detection.
Key finding: The paper proposes a test vector generation technique that selectively toggles primary inputs based on their relative impact on switching activity of rare nets rather than exhaustive or Hamming-distance-based search,... Read more
Key finding: This work introduces a hybrid ATPG technique combining Genetic Algorithms with Boolean Satisfiability for generating test vectors targeting rare internal nodes that serve as HT triggers. It accounts for feasible payload nodes... Read more
Key finding: The authors apply combinatorial testing to efficiently trigger hardware Trojans in a black-box manner, demonstrating through experiments on AES cryptographic hardware that test suites require only a small number of test... Read more
Key finding: This paper develops a procedure for identifying potential insertion sites for HTs by analyzing gates that have rare controllability and low criticality, and selecting trigger nodes based on rare signal probabilities and... Read more
2. What strategies combine design-for-trust approaches and detection frameworks to mitigate hardware Trojans in third-party designs and complex supply chains?
This theme investigates methodologies that integrate design-time preventive techniques such as logic locking, design-for-trust insertions, and post-manufacturing verification to reduce the risk posed by hardware Trojans in outsourced, third-party intellectual property (IP) cores and complex supply chains. It includes both formal and statistical verification frameworks, feature extraction and multi-level analysis for IP trust verification, and methods for enhancing Trojan detectability through structural modifications. The goal is a scalable, efficient framework to ensure trustworthiness and detect stealthy Trojans in real-world IP reuse scenarios.
Key finding: This work highlights the critical role of hardware-level security foundations for Internet of Things (IoT) devices due to their vulnerability to lifelong deployment without frequent updates. It systematically categorizes... Read more
Key finding: The authors propose ML-FASTrust, a multi-level framework combining flip-flop level structural analysis and combinational logic level quantitative metrics to efficiently detect both explicitly- and implicitly-triggered HTs in... Read more
Key finding: This paper presents a novel partial-scan design test generation technique that synergistically combines Automatic Test Pattern Generation (ATPG) and model checking to activate hardware Trojans in large sequential designs. By... Read more
Key finding: Introduces an automated low-overhead online detection scheme that inserts reliability-focused checking circuits at optimized netlist sites selected via intelligent fault propagation analysis. The scheme enhances detection of... Read more
3. How can hardware Trojan detection be enhanced by hardware reverse engineering, optical imaging, and machine learning approaches across different abstraction levels?
This theme explores advanced hardware Trojan detection by employing reverse engineering workflows, non-destructive backside optical watermark imaging, and machine learning models applied at Register Transfer Level (RTL), gate-level netlists, and physical layouts. The focus is on practical, scalable detection methods that do not require Golden chips or full netlist extraction, improve detection resolution against small Trojans, and interpret complex feature sets for trustworthy decision-making. These approaches address the physical and design-level verification challenges and utilize statistical and explainable AI techniques to improve accuracy and explainability in Trojan detection.
Key finding: ViTaL introduces a statistical validation framework that quantitatively assesses hardware reverse engineering (RE) processes considering manufacturing and RE-induced errors for verifying layout integrity without full netlist... Read more
Key finding: Proposes an innovative technique engineering fill cells in standard cell libraries to be highly reflective in the near-infrared spectrum, enabling optical backside imaging to form a unique watermark pattern of chip layout.... Read more
Key finding: Combines side-channel power analysis with machine learning techniques on acquired power traces and logic test data to build a hardware Trojan detector implementable on low-cost Arduino microcontrollers. The model successfully... Read more
Key finding: Develops an efficient hardware Trojan detection model operating at RTL using a novel single branching feature extracted directly from RTL code, avoiding complex feature extraction from gate-level data. The model, trained and... Read more
Key finding: Proposes a Light Gradient Boosting (LGB) machine learning framework combining structural and SCOAP features along with a novel quartile-based SHAP-driven feature selection method to identify hardware Trojan nets in gate-level... Read more