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Defect Tolerance

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lightbulbAbout this topic
Defect tolerance refers to the ability of a system, particularly in materials science and engineering, to maintain functionality and performance despite the presence of defects or imperfections. This concept is crucial in the design and analysis of resilient structures and components, ensuring reliability and longevity in various applications.
lightbulbAbout this topic
Defect tolerance refers to the ability of a system, particularly in materials science and engineering, to maintain functionality and performance despite the presence of defects or imperfections. This concept is crucial in the design and analysis of resilient structures and components, ensuring reliability and longevity in various applications.

Key research themes

1. How can theoretical principles and computational methods instill and optimize defect tolerance in new semiconductor compounds?

This research area focuses on leveraging first-principles electronic structure calculations and established physical phenomena of defects to inform the design of new semiconductor materials that exhibit defect tolerance. Defect tolerance here means materials that maintain high electrical conductivity and suppress recombination despite the presence of intrinsic or extrinsic defects. This is critical for developing next-generation technologyenabling materials such as halide perovskites, topological insulators, and metal-organic frameworks, where defect behavior diverges from classical semiconductor models. Investigations examine defect formation energies, charge states, and doping possibilities under different chemical potentials and electronic conditions to rationalize and predict defect populations and their impact, informing synthesis and doping strategies that optimize functional performance.

Key finding: Walsh and Zunger demonstrate that defect formation energies depend sensitively on the electronic Fermi level and chemical potentials (growth environment), meaning that intrinsic and extrinsic defect populations are highly... Read more

2. What are state-of-the-art statistical and geometric modeling approaches for tolerance design and analysis in mechanical assemblies to balance quality, cost, and manufacturability?

This theme addresses how statistical and geometric models inform the allocation and optimization of dimensional and geometric tolerances in mechanical assemblies, enabling robust product performance with minimized manufacturing costs. It emphasizes probabilistic characterizations of component variations, assembly stack-ups, and tolerance synthesis under realistic manufacturing uncertainty. Various computational modeling frameworks, including geometric reasoning with manufacturing signature simulation, statistical additive relationships, and cost-based optimization heuristics, have been developed to allocate tolerances effectively to critical features and manage complex tolerance chains concurrently. Efficient computational methods for estimating probabilities of defected products and small quantiles in highdimensional tolerance analyses further support optimization. Such analysis is essential for advanced engineered products (e.g., aircraft wings) requiring reliability assessments under stringent functional requirements.

Key finding: Movahedi presents a statistical framework that allocates tolerances among components in assembled products considering their manufacturing variation modeled by normal distributions. Assuming mutual independence and process... Read more
Key finding: A geometric reasoning model simulates assembly sequences and part variations including manufacturing signatures (systematic surface patterns) along with operating conditions such as gravity and friction. Applied to assemblies... Read more
Key finding: This study compares standard industrial Computer-Aided Tolerancing tools with a novel tolerance simulation approach based on Skin Model Shapes (SMS). SMS incorporates geometric variation models including form, location, and... Read more
Key finding: This work systematically evaluates state-of-the-art simulation methods for statistical tolerance analysis, highlighting challenges such as high dimensionality, nonlinearity of state functions, and disconnected failure domains... Read more
Key finding: This paper proposes a heuristic, flexible algorithm to optimize dimensional tolerances in mechanical assemblies by minimizing the manufacturing cost subject to functional constraints expressed via tolerance chains. The... Read more

3. How can defect characterization and modeling improve understanding and fatigue life prediction in additively manufactured metal materials?

This research pursuit entails experimental and computational characterization of intrinsic defects such as pores, lack-of-fusion voids, and surface roughness in metal parts fabricated by additive manufacturing processes like laser powder bed fusion (L-PBF). It investigates the influence of defect size, morphology, and spatial location—especially near surfaces—on fatigue crack initiation and propagation. Fatigue life models integrate computed stress concentration factors and notch sensitivity concepts with experimental defect metrics to predict stress-life (S-N) behavior. Advanced nondestructive testing, thermal process simulations for defect prediction, and fracture mechanic-based damage tolerance approaches enable quantitative fatigue life estimation supporting reliable design of AM metal components.

by G. Labeas and 
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Key finding: The study integrates thermal process modeling of laser powder bed fusion to localize regions prone to defect formation and characterizes defect features used as inputs in a fracture mechanics based fatigue model. Validation... Read more
Key finding: This paper proposes a fatigue model linking defect size and location relative to component surfaces to fatigue life prediction in LPBF manufactured AlSi10Mg. Using notch theory and finite element derived stress concentrations... Read more

All papers in Defect Tolerance

Advances in our basic scientific understanding at the molecular and atomic level place us on the verge of engineering designer structures with key features at the single nanometer scale. This offers us the opportunity to design computing... more
Abstracf-The fine granularity and reconligurable nature of Field-Programmable Gate Arrays (FPGA's) suggest that defecttolerant methods can be readily applied to these devices in order to increase their maximum economic sizes, through... more
Nanodevices based circuit design will be based on the acceptance that a high percentage of devices in the design will be defective. In this work, we investigate a defect tolerant technique that adds redundancy at the transistor level and... more
In this technical report the suitability of resistive strain sensors was evaluated with particular reference to the monitoring of residual stresses during welding construction of submarine pressure hull and during seabound operation of a... more
In this paper, two equivalence proofs of yield modeling methods for defect-tolerant integrated circuits (ICs) are presented. These proofs are generalizations of those found in [3]; one of the proofs presented in this paper is valid for... more
Nano-crossbar arrays have emerged as area and power efficient structures with an aim of achieving high performance computing beyond the limits of current CMOS. Due to the stochastic nature of nano-fabrication, nano arrays show different... more
In this paper we are going to explore low-level implementation issues for fault-tolerant adders based on multiplexing using majority gates (MAJ). We shall analyze the particular case of a 32-bit ripple carry adder (RCA), as well as... more
Combination of SECDED with a redundancy technique can effectively tolerate a high variation-induced defect rate in future processes. However, while a defective cell in a block can be repaired by SECDED, the block becomes vulnerable to... more
The influence of environment and fatigue waveform shape on crack growth behaviour has been evaluated in a workhorse turbine disc material, Inconel 718, at 600°C through an experimental programme that investigated crack growth from a notch... more
Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyondsilicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated... more
To address the density, scalability, and reliability challenges of emerging nanotechnologies, the authors propose a hierarchy of design abstractions, constructed as reconfigurable fabric regions, whereby designers assign small functional... more
We design extremely flexible ultrahigh-Q diamond-based double-heterostructure photonic crystal slab cavities by modifying the refractive index of the diamond. The refractive index changes needed for ultrahigh-Q cavities with Q ~ 10 7 ,... more
Quantum-dot Cellular Automata (QCA) can be a viable technology for CMPs (chip multi-processors) with thousands of processors. The QCA based reversible logic promises energy efficient design of the digital circuits. However, the... more
for help during the power-dependent emission measurement. We thank the Microfabrication Laboratories and the National Center for Electron Microscopy for the use of their facilities.
In this paper, an efficient method to achieve defect-tolerance with embedded single-port word-oriented RAM is presented. The defect tolerance of the RAM is based on a hierarchical redundancy technique employing a self-test and... more
This paper describes the implementation of the Advanced Encryption Standard Algorithm, Rijndael, in a new nanoscale technology, called CMOL. This technology consists of an array of conventional CMOS gates and a wiring network, which... more
The fabrication of crossbar memories with sublithographic features is expected to be feasible within several emerging technologies; in all of them, the nanowire (NW) decoder is a critical part since it bridges the sublithographic wires to... more
We present a CAD framework for CMOL, a hybrid CMOS/ molecular circuit architecture. Our framework first transforms any logically synthesized circuit based on AND/OR/NOT gates to a NOR gate circuit, and then maps the NOR gates to CMOL. We... more
Nature utilizes self-assembly to fabricate structures on length scales ranging from the atomic to the macro scale. Selfassembly has emerged as a paradigm in engineering that enables the highly parallel fabrication of complex, and often... more
Quantum-dot Cellular Automata (QCA) can be a viable technology for CMPs (chip multi-processors) with thousands of processors. The QCA based reversible logic promises energy efficient design of the digital circuits. However, the... more
It is well recognized that novel computational models, devices and technologies are needed in order to sustain the remarkable advancement of CMOS-based VLSI circuits and systems. Regardless of the models, devices and technologies, any... more
Producing reliable nanosystems requires effectively addressing the high defect densities projected for nanotechnologies. Defect avoidance methodologies based on reconfiguration offer a promising solution to achieve defect tolerance. The... more
To address the density, scalability, and reliability challenges of emerging nanotechnologies, the authors propose a hierarchy of design abstractions, constructed as reconfigurable fabric regions, whereby designers assign small functional... more
This paper presents an efficient technique for designing high defect tolerance Static Random Access Memories (SRAMs) with significantly low power consumption. The new approach requires drastically lower area overhead, simpler encoding... more
We address the challenge of implementing reliable computation of Boolean functions in future nanocircuit fabrics. Such fabrics are projected to have very high defect rates. We overcome this limitation by using a combination of cheap but... more
Molecular electronics-based devices are assumed to include at least 10 10 gate-equivalents/cm 2 and defect densities as high as 10%; novel test strategies are necessary to efficiently test and diagnose these nanoscale devices.... more
Jack-up platforms are to an increasing extent being considered for use as long-term production support structures. The implications of this new application for structural integrity assessment and maintenance are significant. Traditional... more
Recent successes in the development and self-assembly of nanoelectronic devices suggest that the ability to manufacture dense nanofabrics is on the near horizon. However, the tremendous increase in device density of nanoelectronics will... more
Two aspects of the impact of reconfiguration logic on the optimization of defect-tolerant integrated circuits (ICs) are analyzed. An important consequence to design decisions of neglecting reconfiguration logic is presented. Expressions... more
This paper presents a theoretical expression to evaluate the test quality of hierarchical defect-tolerant integrated circuits. This expression, which is developed for circuits with two levels of hierarchy, is based on a defect model with... more
In this paper, two equivalence proofs of yield modeling methods for defect-tolerant integrated circuits (ICs) are presented. These proofs are generalizations of those found in [3]; one of the proofs presented in this paper is valid for... more
We present a method to accelerate the search for the number of spares to be included in defect tolerant integrated circuits. Our method is obtained by bringing two modifications to a conventional evaluation method. The main motivations... more
Computation-intensive multimedia applications are emerging on mobile devices.System-on-Chip (SoC) offers high performance at a decreased size for these devices. SoC often integrates tens of cores and uses Network-on-Chip (NoC) as its... more
We developed strategies based on self-assembly principles to etch substrates patterned with monolayer resists with high selectivity and etch directionality. Our strategies exploit the defined composition and order of these ultrathin... more
We developed strategies based on self-assembly principles to etch substrates patterned with monolayer resists with high selectivity and etch directionality. Our strategies exploit the defined composition and order of these ultrathin... more
This research concentrates on the area of fault tolerant circuit implementation in a field programmable type architecture. In particular, an architecture called the Cell Matrix, presented as a fault tolerant alternative to field... more
Chemically Assembled Electronic Nanotechnology (CAEN) using bottom-up approach for digital circuit design has imposed new dimensions for miniaturization of electronic devices. Crossbar structures or Nanofabrics using silicon nanowires and... more
Several technologies with sub-lithographic features are targeting the fabrication of crossbar memories in which the nanowire decoder is playing a major role. In this paper, we suggest a way to reduce the decoder size and keep it defect... more
Recent successes in the development and self-assembly of nanoelectronic devices suggest that the ability to manufacture dense nanofabrics is on the near horizon. However, the tremendous increase in device density of nanoelectronics will... more
Mustafa Altun, Marc D. Riedel, and Claudia Neuhauser University of Minnesota, USA E.mail: $altu0006, mriedel, neuha001% @umn.edu ... ABSTRACT In this study, we apply a novel synthesis technique for implementing robust digital computation... more
Accurate residual fatigue life predictions under variable amplitude (VA) loading are essential to maximize the time between the required inspections in defect-tolerant structures. However, this is not a trivial task for real structural... more
As we move from deep submicron technology to nanotechnology for device manufacture, the need for defect-tolerant architectures is gaining importance. This is because, at the nanoscale, devices will be prone to errors due to manufacturing... more
As we move from deep submicron technology to nanotechnology for device manufacture, the need for defect-tolerant architectures is gaining importance. This is because, at the nanoscale, devices will be prone to errors due to manufacturing... more
As we move from deep submicron technology to nanotechnology for device manufacture, the need for defect-tolerant architectures is gaining importance. This is because, at the nanoscale, devices will be prone to errors due to manufacturing... more
Nano-computing in the form of quantum, molecular and other computing models is proliferating as we scale down to nanometer fabrication technologies, and 2015 is considered by many industry experts as the deadline for straight forward... more
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