Hardware Attack Mitigation Techniques Analysis

2008

As the value of data on computing systems increases and operating systems become more secure, physical attacks on computing systems to steal or modify assets become more likely. This technology requires constant review and improvement, just as other competitive technologies need review to stay at the leading edge. This paper describes known physical attacks, ranging from simple attacks that require little skill or resource, to complex attacks that require trained, technical people and considerable resources. Physical security methods to deter or prevent these attacks are presented. The intent is to match protection methods with the attack methods in terms of complexity and cost. In this way cost effective protection can be produced across a wide range of systems and needs. Specific technical mechanisms now in use are shown, as well as mechanisms proposed for future use. Common design problems and solutions are discussed with consideration for manufacturing.

2020

Information Systems, increasingly present in a world that goes towards complete digitalisation, can be seen as complex systems at the base of which is the hardware. When dealing with the security of these systems to stop possible intrusions and malicious uses, the analysis must necessarily include the possible vulnerabilities that can be found at the hardware level, since their exploitation can make all defences implemented at web or software level ineffective. In this paper, we propose a meaningful and comprehensive taxonomy for the vulnerabilities affecting the hardware and the attacks that exploit them to compromise the system, also giving a definition of Hardware Security, in order to clarify a concept often confused with other domains, even in the literature.

An important direction of improving security of computer systems is detection of Trojan horse hardware. A Trojan horse is a malicious altering of hardware specification or implementation in such a way that its functionality is altered under a set of conditions defined by the attacker. The paper presents a technique for designing secure systems that can detect an active Trojan that distorts or manipulates their proper operation. The technique is based on utilizing specific information about the system's behavior, which is known to the designer of the system and/or is hidden in the functional specification of the system. A case study of the proposed technique conducted on an arithmetic unit of a microprocessor is provided. The study indicated a high level of Trojan detection with a small hardware overhead.

Today's integrated circuits (ICs) are vulnerable to hardware Trojans, which are malicious alterations to the circuit, either during design or fabrication. The interventions of human in production of Hardware resources have given room for possible modification of hardware components, so as to achieve some malicious aims. This modification help with possible loop holes in the hardware component for later attack. Due to the increase in popularity aim of attacks using embedded Trojan horse programs into chips, attacker are more likely to suppress them with malicious program, also notwithstanding the increase in disintegration of the design and manufacturing process of our microelectronic products (ICs), we should not only concern about inclusion of unplanned, undesirable hardware features (" bugs "), rather about inclusion of planned malicious hardware features: " Trojan Horses, " which act as spies or guerrillas. This paper presents a Model of the fundamental attacks and possible detection techniques of Hardware Trojan. The result of the research has shown a great significance in education and for further researches.

Security and Privacy, 2019

Malware target a vulnerability, bug or loophole in software to exploit the system, escalate privileges, extract inaccessible data, or execute code for malicious purpose. We can assert that over the period of time, both hardware and software have evolved and so are their vulnerabilities. But most of the vulnerabilities identified or researched are software oriented. On similar lines, there can be vulnerabilities in the hardware architecture that can be exploited, hidden from upper layer securities like operating system (OS) reference monitor, antivirus, etc. It is difficult to trace the vulnerabilities in the hardware primarily due to complex architecture and difficulties to observe the effects of operations performed across the system. Just like the software, the hardware architecture can also be exploited to develop malware and to gain access to sensitive data. This paper discusses the attacks that exploit the operations performed at the hardware level. We have discussed the different exploits that use the hardware architecture to extract data, their limitations and the future of hardware architecture based exploits. At the end, the data extraction process is validated through our implementation of one of the hardware architecture based exploits. We question about the impact on system security if the hardware architecture is exploited. K E Y W O R D S architectural vulnerability, hardware attacks, micro-architectural attacks, side channel 1 INTRODUCTION All the operations on a computer, at the lowest level, are hardware dependent. Over the course of time computers have evolved from simple computing machines to very complex machines, thanks to the evolution of software and the hardware that drives it. As the hardware and software have evolved, so are the vulnerabilities associated with them. It is commonly observed that software vulnerabilities are detected frequently and patched, but same is not the case with hardware vulnerabilities. Vulnerabilities in hardware architecture are not much researched as extensively as software, apart from its developers, in the cyber security domain. This leads to many hardware-based attacks such as • Rowhammer, 1,2 an attack that exploits bit flipping in DRAM due to continuous access, which bypasses the memory isolation and breaks security boundaries. • Exploitation of the instruction cache. 3 • Side channel attacks that can extract data using a nontraditional way of communication. 4-6

International Journal of VLSI Design & Communication Systems, 2018

The latest innovation technology in computing devices has given a rise of compact, speedy and economical products which also embeds cryptography hardware on-chip. This device generally holds secret key and confidential information, more attention has been given to attacks on hardware which guards such secure information. The attacker may leak secret information from symmetric crypto-hardware (AES, DES etc.) using side-channel analysis, fault injection or exploiting existing test infrastructure. This paper examines various DFT based attack implementation method applied to cryptographic hardware. The paper contains an extensive analysis of attacks based on various parameters. The countermeasures are classified and analyzed in details.

Electronics

Cyber-Physical system devices nowadays constitute a mixture of Information Technology (IT) and Operational Technology (OT) systems that are meant to operate harmonically under a security critical framework. As security IT countermeasures are gradually been installed in many embedded system nodes, thus securing them from many well-know cyber attacks there is a lurking danger that is still overlooked. Apart from the software vulnerabilities that typical malicious programs use, there are some very interesting hardware vulnerabilities that can be exploited in order to mount devastating software or hardware attacks (typically undetected by software countermeasures) capable of fully compromising any embedded system device. Real-time microarchitecture attacks such as the cache side-channel attacks are such case but also the newly discovered Rowhammer fault injection attack that can be mounted even remotely to gain full access to a device DRAM (Dynamic Random Access Memory). Under the light of the above dangers that are focused on the device hardware structure, in this paper, an overview of this attack field is provided including attacks, threat directives and countermeasures. The goal of this paper is not to exhaustively overview attacks and countermeasures but rather to survey the various, possible, existing attack directions and highlight the security risks that they can pose to security critical embedded systems as well as indicate their strength on compromising the Quality of Service (QoS) such systems are designed to provide.

International Journal of Multimedia Intelligence and Security, 2019

Hardware security threats have gained a tremendous attention where extensive research efforts have been expended toward developing effective countermeasures. These threats can be categorised into five main attacks which are: reverse engineering, side-channel analysis, intellectual property (IP) cores piracy/IC overbuilding, counterfeiting, and hardware Trojans. This paper investigates the most efficient state-of-the-art techniques that are used to thwart main hardware attacks. Reported work in the literature proposed various countermeasures, where obfuscation, camouflaging, and physically unclonable functions (PUFs) are considered the most powerful and effective methods. In obfuscation technique, the chip will be locked and it will not function properly unless the correct secret key is supplied. This paper addresses also camouflaging countermeasure which is a layout-based technique that is used to protect IP cores. Additionally, this paper provides a detailed study on silicon PUFs, where they can be classified into weak and strong PUFs. In this paper, various PUF architectures will be discussed along with the design constraints.

2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016

to the best of my knowledge, my thesis does not infringe upon anyone's copyright, nor violate any proprietary rights. Any ideas, techniques, quotations, and material appertaining to other people included in my thesis, published or otherwise, are fully acknowledged in accordance with standard referencing practices. Furthermore, to the extent that I have included copyrighted material that surpasses the bounds of fair dealing within the meaning of the Canada Copyright Act, I certify that I have obtained a written permission from the copyright owner(s) to include such material(s) in my thesis and have included copies of such copyright clearances in my appendix. I certify that I have obtained written permission from the copyright owner(s) to include the above published materials in my thesis. I certify that the above material describes work completed during my registration as graduate student at the University of Windsor. I declare that this is a true copy of my thesis, including any final revisions, as approved by my thesis committee and the Graduate Studies office, and that this thesis has not been submitted for a higher degree to any other University or Institution. v ABSTRACT Scan based Design for Test (DfT) schemes have been widely used to achieve high fault coverage for integrated circuits. The scan technique provides full access to the internal nodes of the deviceunder-test to control them or observe their response to input test vectors. While such comprehensive access is highly desirable for testing, it is not acceptable for secure chips as it is subject to exploitation by various attacks. In this work, new methods are presented to protect the security of critical information against scan-based attacks. In the proposed methods, access to the circuit containing secret information via the scan chain has been severely limited in order to reduce the risk of a security breach. To ensure the testability of the circuit, a built-in self-test which utilizes an LFSR as the test pattern generator (TPG) is proposed. The proposed schemes can be used as a countermeasure against side channel attacks with a low area overhead as compared to the existing solutions in literature. vi DEDICATION I would like to dedicate this thesis to my family my late grandfather Ainshi Lal Mehta and late grandmother Lajwanti Mehta. Your blessings and the values you taught me made this possible. I miss you a lot and still remember the good old days. In addition to this, I would like to dedicate my work to my parents and my cousin brother. Special thanks to my parents, Mr. Sanjay Mehta and Mrs. Sonia Mehta, for always supporting me to pursue my master's degree and my loving, sweet younger sister, Manya Mehta, who is very good and her constant motivation helped me to achieve my master's degree. No matter how far I go in my life, this would not have been possible without all of you. I would also like to thank my cousin brother, Dr. Bhuvanender Vashist (Sonu Bhaiya), for always motivating me to continue my studies and making me realize the importance of a degree from abroad. This would never have been possible had you not given me your emotional support. You have always stood as my shield against all problems I have faced and provided the best and the right guidance. I thank God for having you in my life and will love you forever. Last but not the least, I would like to thank God for the person that I am today and making this master's degree possible. vii ACKNOWLEDGEMENTS I would like to thank my supervisor, Dr. Rashid Rashidzadeh, and advisor, Dr. Majid Ahmadi, their unbounded support, motivation, constructive comments, and motivation throughout my master's degree helped address even the most basic of questions. Without their support, I could not have completed this degree. The constructive feedback which they provided helped polish my work. I would also like to thank my other committee members, Dr.