Papers by Mohammad Alhawari
Reconfigurable, Switched-Capacitor Power Converter for IoT
The IoT Physical Layer, 2018
This chapter introduces an efficient reconfigurable, multiple voltage gain switched-capacitor DC–... more This chapter introduces an efficient reconfigurable, multiple voltage gain switched-capacitor DC–DC buck converter as part of a power management unit for wearable IoTs. The switched-capacitor converter has an input voltage of 0.6–1.2 V generated from an energy harvesting source. The switched-capacitor converter utilizes pulse frequency modulation to generate multiple regulated output voltage levels, namely 1, 0.8 and 0.6 V based on two reconfigurable bits over a wide range of load currents from 10 \(\upmu \)A to 800 \(\upmu \)A. The switched-capacitor converter is designed and fabricated in 65 nm low-power CMOS technology and occupies an area of 0.493 mm\(^2\). The design utilizes a stack of MIM and MOS capacitances to optimize the circuit area and efficiency. The measured peak efficiency is 80\(\%\) at a load current of 800 \(\upmu \)A and regulated load voltage of 1 V.
Analog Circuits and Signal Processing, 2017
As explained in Chap. 3, an inductor-based DC-DC converter is widely used in energy harvesting ap... more As explained in Chap. 3, an inductor-based DC-DC converter is widely used in energy harvesting applications due to its high efficiency [67, 76]. The efficiency of the converter depends on the inductor quality factor, the technology used, losses in the converter and the control circuit. In addition, the synchronous inductor-based DC-DC converter is used to reduce the losses associated with the diode in the asynchronous converter [72]. However, the synchronization (using the ZCS control) between the switches in the synchronous converter is essential to maintain a high efficiency [81]. In order to maximize the efficiency of the boost converter, losses in the circuit should be carefully analyzed. Conduction and switching losses of the NMOS, PMOS, and series resistance of the inductor contribute in the overall losses budget. In addition, leakage current through the switches affects the efficiency. Further, the power consumption and the leakage of the control circuitry should be minimized. ZCS control plays a major role in maintaining the efficiency of the inductor-based converter. Figure 4.1 shows the synchronous inductor-based boost converter used for TEG harvester along with the ZCS. As discussed in Chap. 3, the ZCS is used to turn off the PMOS switch when the inductor current reaches zero so that the charge in the output capacitor is preserved. Different techniques can be implemented to detect the zero current point such as sensing the voltage polarity across the PMOS switch using a comparator-controlled MOSFET (active diode) as shown in Fig. 4.2a [67, 82]. However, this technique requires a very fast comparator to close the PMOS switch once the polarity across the PMOS is flipped. Any delay in the comparator could result in depleting the charge from the output capacitor and degrading efficiency. Further, in [83], the zero current is detected by forming an inductor current loop using a switch connected in parallel with the inductor as shown in Fig. 4.2b. This switch is activated at the end of the discharging phase so that the polarity of the
2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), 2020
Time-domain (TD) accelerators leverage both digital and analog features, thereby enabling energy-... more Time-domain (TD) accelerators leverage both digital and analog features, thereby enabling energy-efficient computing and scaling with CMOS technology. This paper reviews state-of-the-art TD accelerators and discusses system considerations and hardware implementations, including the spatially unrolled and recursive TD architectures. Additionally, the paper analyzes the energy and area efficiency of the TD architectures for varying input resolutions and network sizes. This analysis provides insight for designers into how to choose the appropriate TD approach for a particular application.
Introduction to Power Management
Analog Circuits and Signal Processing, 2020
The advancements in CMOS technology have enabled the evolution of low power circuits and systems ... more The advancements in CMOS technology have enabled the evolution of low power circuits and systems in many applications including wearable biomedical devices. It allows the devices to operate at sub-microwatt power range and opens up a new era of the Internet of things. These new devices require small size with near perpetual lifetime. However, the traditional battery technology is not scaling at the same rapid rate as the shrinking of transistor size. Therefore, there is a need for efficient management of the power source to reduce both dynamic and leakage power of the device and a need to increase the energy sources via energy harvesting. The introduction of energy harvesting brings some design challenges since the harvested energy has variable voltage and it depends on the availability and size of the harvester. Therefore, a power management unit is needed to manage the energy transfer from the harvester and control the power distribution and consumption of different blocks in the device.
Interface Circuits for Thermoelectric Generator
In this chapter, recent work is presented on different interface circuits for TEG energy harvesti... more In this chapter, recent work is presented on different interface circuits for TEG energy harvesting systems. Further, the inductor-based boost converter is introduced as the main interface circuit for TEG harvesting systems. After that, different digital control circuits are explored for inductor-based boost converter. This includes zero current control, TEG polarity circuits, maximum power point tracking methods, and startup circuits.
Energy Combiner and Power Manager for Multi-Source Energy Harvesting
In this chapter, recent work in multi-source energy harvesting system is compared. This includes ... more In this chapter, recent work in multi-source energy harvesting system is compared. This includes different energy combining techniques used to deliver the energy from multiple energy harvesting sources to the load. In addition, the design of an efficient energy combiner is proposed with power manager to form a complete energy harvesting system. Furthermore, a sleep mode operation for low power processor is explained which is necessary when the input energy is variable.
Angular-Momentum Biased Circulator With Locally Generated Modulation
IEEE Transactions on Microwave Theory and Techniques, 2021
This article presents a novel type of time-modulated magnetless circulators, where modulation is ... more This article presents a novel type of time-modulated magnetless circulators, where modulation is generated locally at each modulated element through a network of local oscillators instead of a central source and a complex distribution network based on phase shifters and filters. The design follows the angular-momentum approach, and the modulation signals are generated from three cross-coupled oscillators interconnected through transmission lines in a ring topology to phase lock and attain the necessary phase difference of 120°. The oscillators are interwound with the circulator circuit by designing them to operate in a differential mode, in contrast to the common mode of the circulator circuit, allowing natural isolation between the RF and modulation paths. Two prototypes were built to test the design. An initial preliminary printed-circuit-board prototype was fabricated to test the common-differential mode topology with modulation signals generated off the board. The design was tested at 1.78 GHz, showing isolation of more than 20 dB, insertion loss of 5.5 dB, 2.6% bandwidth, and power handling of 21 dBm. A final prototype was fabricated to test a fully autonomous circulator, with the modulation signals generated locally at each modulated tank. The final design was tested at 1.65 GHz, showing isolation greater than 20 dB, insertion loss of 5.3 dB, 4.8% bandwidth, and power handling of 25.52 dBm. The results open a path for a new class of autonomous time-modulated devices without the need for complicated modulation networks and with an ability to incorporate a large number of modulated elements.
A Charge Pump Based Power Management Unit With 66%-Efficiency in 65 nm CMOS
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018
This paper presents a single stage power management unit that includes an enhanced stage-switch D... more This paper presents a single stage power management unit that includes an enhanced stage-switch Dickson charge pump (DCP) to boost and regulate a low input voltage. A new switching mechanism is presented to significantly reduce the losses encountered in conventional DCP switches. Frequency and stage modulation are utilized in the proposed design. The stage modulation provides different gain levels (coarse) and the frequency modulation tunes the voltage level and regulates the output voltage based on a pre-determined reference voltage. Using four stages charge pump, silicon measurement results in 65 nm CMOS technology show a maximum efficiency of 66% at input voltage of 0.7 V and output power of 27 μW. The system supports a range of load current between 0.1 μA − 34 μA with a maximum operating frequency of 1.8MHz. The proposed system supports an input voltage range from 0.55 to 0.7 V which can be used in energy harvesting applications such as solar and thermal harvesting.
2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), 2020
This paper presents a digitally-controlled, CMOS analog memory circuit that provides several anal... more This paper presents a digitally-controlled, CMOS analog memory circuit that provides several analog stable operating points based on the laddered inverter quantizer (LIQAF) circuit. Two input digital pulses set the stored analog level by moving the stable operating point up or down through charging or discharging the output node, respectively. The proposed circuit achieves its stable operating levels through nonlinear, continuoustime feedback using only a single supply voltage. We present SPICE simulation results for an 8-level version of the multistable circuit in a 65 nm CMOS process. The results demonstrate that the proposed circuit can operate at low-power consumption from a wide range of supply voltages with robust operation across process and temperature variations. The proposed circuit has the potential to be integrated into the grid array of analog neural networks.
Characterization of RF energy harvesting at 2.4 GHz
2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2017
This paper presents a comprehensive study on RF energy harvesting process at a frequency of 2.4GH... more This paper presents a comprehensive study on RF energy harvesting process at a frequency of 2.4GHz using P21XXCSR-EVB evaluation board from Powercaset. The study is carried out by considering several types of antennas, varying distances from the transmitting source at different input and output power values. The maximum distance at which the harvesting kit can regulate the output voltage of 3.4V is 116 cm using 10dBi omnidirectional antenna. Further, the harvesting kit can produce an output power of 4mW using a 5dBi dipole antenna at 10 cm away from the source with a maximum circuit efficiency of 55%. The demonstration of energy harvesting is presented by powering an LED dimming circuit. This study could be helpful for researchers to design circuits and systems in RF energy harvesting area.
A Comparative Analysis of Time-Domain and Digital-Domain Hardware Accelerators for Neural Networks
2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021
This paper presents a comprehensive analysis of hardware accelerators for neural networks in both... more This paper presents a comprehensive analysis of hardware accelerators for neural networks in both the digital and time domains, where the latter includes spatially unrolled (SU) and recursive (REC) architectures. All accelerators are implemented and synthesized in a 65nm CMOS technology. An identical neural network model is implemented in the digital and time domain for comparative purposes in terms of throughput, power consumption, area, and energy efficiency. Post-synthesis results show that SU achieves the highest energy efficiency of 145 TOp/s/W with a throughput of 4 GOp/s. The digital core is the fastest among other cores, whereas REC is the slowest but is the most area-efficient, occupying 0.114 mm2. SU is more suited for applications with stringent power constraints and average performance, while REC is better suited for applications where the area is the most important requirement and the throughput is less significant. In contrast, the digital core is preferable for large neural networks and critical applications that require high performance.
Analysis of Artifacts Removal Techniques in EEG Signals for Energy-Constrained Devices
2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2021
This paper analyzes and evaluates various denoising techniques, including Wavelet Transform and M... more This paper analyzes and evaluates various denoising techniques, including Wavelet Transform and Moving Average Filter methods for removing ocular and motion artifacts from EEG signals. The performance of each technique is benchmarked in terms of signal-to-noise ratio (SNR) and normalized mean squared error (NMSE) on available EEG databases, including Bonn and Motion-Artifact Contaminated EEG databases. Simulation results show that the Wavelet Transform using the SURE Shrink algorithm with the hard thresholding rule has the best performance for removing ocular artifacts in intracranial EEG. In contrast, the Wavelet Transform using the universal threshold shrinkage rule with hard thresholding is the preferred method for removing motion artifacts in scalp EEGs. This study is an essential step toward more advanced work to achieve real-time, and low-cost denoising methods for energy-constrained devices.
International Journal of Multimedia Intelligence and Security, 2019
Hardware security threats have gained a tremendous attention where extensive research efforts hav... more Hardware security threats have gained a tremendous attention where extensive research efforts have been expended toward developing effective countermeasures. These threats can be categorised into five main attacks which are: reverse engineering, side-channel analysis, intellectual property (IP) cores piracy/IC overbuilding, counterfeiting, and hardware Trojans. This paper investigates the most efficient state-of-the-art techniques that are used to thwart main hardware attacks. Reported work in the literature proposed various countermeasures, where obfuscation, camouflaging, and physically unclonable functions (PUFs) are considered the most powerful and effective methods. In obfuscation technique, the chip will be locked and it will not function properly unless the correct secret key is supplied. This paper addresses also camouflaging countermeasure which is a layout-based technique that is used to protect IP cores. Additionally, this paper provides a detailed study on silicon PUFs, where they can be classified into weak and strong PUFs. In this paper, various PUF architectures will be discussed along with the design constraints.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019
This paper presents a single-stage power management unit to boost and regulate a low supply volta... more This paper presents a single-stage power management unit to boost and regulate a low supply voltage for CMOS system-on-chip (SoC) applications. It consists of low-leakage, enhanced Dickson charge pump (DCP) that utilizes both stage and frequency modulation (FM) techniques to achieve high efficiency and lower area. In addition, the proposed design uses an enhanced stage-switch structure for the charge pump, which significantly reduces the cross-stage leakage. A stage number controller is used to control the gain of the charge pump by changing the number of stages based on the desired output voltage. FM is utilized to further fine-tune the output voltage through a closed-loop control based on a predetermined reference voltage. Silicon measurement results for the four-stage charge pump in 65-nm CMOS technology show a maximum end-to-end efficiency of 66% at an input voltage of 0.7 V and an output power of 27 W. The proposed design achieved more than a 100x reduction in leakage compared to traditional DCP. The system supports a range of load currents between 0.1 and 34 A with a maximum operating frequency of 1.8 MHz. The proposed system supports an input voltage range of 0.55-0.7 V which makes it an excellent candidate for solar and thermal energy-harvesting applications targeting low-power internet-of-things SOC.
IEEE Sensors Journal, 2018
Resistive Random-Access memory (RRAM) technology has been gaining importance due to scalability, ... more Resistive Random-Access memory (RRAM) technology has been gaining importance due to scalability, low power, non-volatility, and the ability to perform in-memory computing. The RRAM sensing applications have also emerged to enable single RRAM technology platforms which include sensing, data storage, and computing. This paper reports on sol-gel drop coated low-power µ-thick Ag/TiO2/Cu memristor, named MemSens, developed for radiation sensing. MemSens exhibits a bipolar memristive switching behavior within a small voltage window, ranging up to +0.7 V for the turn-ON, and down to-0.2 V for the turn-OFF. Under these operating conditions, MemSens has 67% less switching voltage, 20% drop in ON switching current, 75% reduced active area and > 3x improved device endurance, compared to the best characteristics reported in the literature for µ-thick memristors. The device is tested under direct exposure to ionizing Cs-137 662keV γ-rays, during which a significant increase in the electrical conductivity of the device is observed. MemSens circuit is proposed to allow a relatively real time and cost-effective radiation detection. This provides a first insight to the advancement of reliable memristors that could potentially be deployed in future low-power radiation sensing technologies for medical, personal protection and other field applications.
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018
This paper presents an area-and power-efficient dual-output switched capacitor (DOSC) dc-dc buck ... more This paper presents an area-and power-efficient dual-output switched capacitor (DOSC) dc-dc buck converter for wearable biomedical devices. The DOSC converter has an input voltage range between 1.05 and 1.4 V and generates two simultaneous regulated output voltages of 1 and 0.55 V. The DOSC consists of two main blocks: a switched capacitor regulator and an adaptive time multiplexing (ATM) controller. The switched capacitor regulator generates a single regulated voltage using pulse frequency modulation based on a predetermined reference voltage. In addition, the ATM controller generates two simultaneous output voltages and eliminates the reverse current using pulse width modulation during the switching between the output voltages. Addressing the reverse current problem is important to reduce the output voltage droop and improve the performance. The proposed converter supports load currents of 10-350 µA and 1-10 µA at load voltages of 1 and 0.55 V, respectively. The DOSC circuit is fabricated in 65-nm CMOS, and it occupies an active area of 0.27 mm 2. Measured results show that a peak efficiency of 78% is achieved at a load power of 300 µW.
A 0.23 mW, On-Chip, self-calibrating RF amplitude detector in 65 nm CMOS
2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), 2016
We present an RF amplitude detector with a conversion gain of −3 V/V for RF amplitude range 0 to ... more We present an RF amplitude detector with a conversion gain of −3 V/V for RF amplitude range 0 to 0.6 Vp in 65nm CMOS. On-chip self-calibration structure that automatically corrects the variations within the RF detector itself is proposed. Silicon measurement results show the self-calibration structure improves the detection error of the non-calibrated RF amplitude detector to less than 10% at only 0.23mW power consumption.
An efficient thermal energy harvesting and power management for μWatt wearable BioChips
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016
This paper presents an efficient thermal energy harvesting IC (EHIC) that supports a battery-less... more This paper presents an efficient thermal energy harvesting IC (EHIC) that supports a battery-less μWatt system-on-chips. The EHIC consists of an inductor-based DC-DC converter that boosts a low input voltage to a suitable output voltage level. Further, a switched capacitor buck converter is utilized to regulate the boost converter output voltage and to support multiple output voltage levels, namely 0.6V, 0.8V and 1V. In low energy mode and to enhance the efficiency, the EHIC is capable of bypassing the switched capacitor so that the load is driven directly from the boost converter. The prototype chip is fabricated in 65nm CMOS and occupies an area of less than 0.46mm2. Measured results confirm an efficiency of 65% at 0.6V output voltage and 42μW. In addition, the end-to-end peak efficiency is 71% at 0.8V output voltage and 182μW.
An Efficient Switched-Capacitor DC-DC Buck Converter for Self-Powered Wearable Electronics
IEEE Transactions on Circuits and Systems I: Regular Papers, 2016
This paper introduces an efficient reconfigurable, multiple voltage gain switched-capacitor dc-dc... more This paper introduces an efficient reconfigurable, multiple voltage gain switched-capacitor dc-dc buck converter as part of a power management unit for wearable electronics. The proposed switched-capacitor converter has an input voltage of 0.6 V to 1.2 V generated from an energy harvesting source. The switched-capacitor converter utilizes pulse frequency modulation to generate multiple regulated output voltage levels, namely 1 V, 0.8 V, and 0.6 V based on two reconfigurable bits over a wide range of load currents from 10 μA to 800 μA. The switched-capacitor converter is designed and fabricated in 65-nm low-power CMOS technology and occupies an area of 0.493 mm2. The design utilizes a stack of MIM and MOS capacitances to optimize the circuit area and efficiency. The measured peak efficiency is 80% at a load current of 800 μA and regulated load voltage of 1 V.
An all-digital, CMOS zero current switching circuit for thermal energy harvesting
2015 European Conference on Circuit Theory and Design (ECCTD), 2015
This paper introduces an all digital, CMOS zero current switching (ZCS) circuit that enables a wi... more This paper introduces an all digital, CMOS zero current switching (ZCS) circuit that enables a wide dynamic and a fine resolution zero current detection range for high gain (50 mV input to 1.35 V output) inductor-based DC-DC converter. Using only a 3-bit design, more than 1.5 μs dynamic range with 50 ns delay resolution is achieved. The prototype chip is designed and simulated using 65 nm low-power CMOS technology and occupies less than 0.04 mm2 area. Post-layout SPICE simulations confirm that 85% efficiency can be achieved for the overall system. The proposed circuit is part of a system that targets energy harvesting from human body thermal energy to enable long lifetime operation for wearable and biomedical devices.
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Papers by Mohammad Alhawari