Synthesis of Delay-Verifiable Combinational Circuits

We consider the problem of testing for delay faults in macrobased circuits. Macro-based circuits are obtained as a result of technology mapping. Gate-level fault models cannot be used for such circuits, since the implementation of a macro may not have an accurate gate-level counterpart, or the macro implementation may not be known. Two delay fault models are proposed for macro-based circuits. The first model is analogous to the gatelevel gross delay fault model. The second model is analogous to the gate-level path delay fault model. We provide fault simulation procedures, and present experimental results.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991

It is known that circuit delays and timing skews in input vector changes influence choice of tests to detect delay faults. Tests for stuck-open faults in CMOS logic circuits can also be invalidated by circuit delays and timing skews in input vector changes. Tests that detect modeled faults independent of the delays in the circuit under test are called robust tests. In this paper we propose an integrated approach to the design of combinational logic circuits in which all path delay faults and multiple line stuck-at, transistor stuck-open faults are detectable by robust tests. We also demonstrate that the proposed method guarantees the design of CMOS logic circuits in which all path delay faults are locatable.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992

Reliability and testability considerations are grow ing in importance in large-scale computing. In order to test chips produced from sophisticated fabrication processes for correctness, high fault coverages under enhanced fault models, such as multiple stuck-at faults and delay faults, have to be obtained.

2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390), 2000

The number of physical paths in a carry save or modified Booth multiplier, as well as in a non restoring cellular array divider is prohibitively large for testing all paths for delay faults. Besides, neither all paths are robustly testable nor a basis consisting of SPP-HFRT paths exists.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1997

In this paper, we present methods for synthesizing multilevel asynchronous circuits to be both hazard free and completely testable. Making an asynchronous two-level circuit hazard free usually requires the introduction of either redundant or nonprime cubes or both. This adversely affects the circuit's testability. However, using extra inputs, which is seldom necessary, and a synthesis-for-testability method, we convert the two-level circuit into a multilevel circuit that is completely testable. To avoid the addition of extra inputs as much as possible, we intro duce new exact minimization algorithms for hazard-free two-level logic where we first minimize the number of redundant cubes and then minimize the number of nonprime cubes. We target both the stuck-at and robust path delay fault models using similar methods. However, the area overhead for the latter may be slightly higher than for the former.

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753), 2004

When time is incorporated in the specification of discrete systems, the complexity of verification grows exponentially. When the temporal behavior is specified with symbols, the verification problem becomes even more difficult. This paper presents a formal verification technique for timed circuits with symbolic delays. The approach is able to provide a set of sufficient linear constraints on the symbols that guarantee the correctness of the circuit. The applicability of the technique is shown by solving the problem of automatic discovery of linear constraints on input and gate delays that guarantee the correct behavior of asynchronous circuits.

IEEE Journal of Solid-State Circuits, 1996

Abstruct-A complete set of rules is presented for timing verification of domino-style dynamic circuits. These rules include identification of dynamic nodes, generation of accurate timing constraints based on the operating environment of the gate and verification as an enhanced part of a complete timing veacation process. This methodology has been implemented in a new static timing verifier and used to verify microprocessor circuits.

Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001

Delay-insensitive (DI) circuits are a class of asynchronous circuits that operate correctly regardless of delays in components or wires. We model such circuits using their traces, or sequences of events (signal transitions) that occur during the operation of the circuit. As shown in [16], [9], and [18], DI circuits can be characterized by certain properties regarding swapping consecutive events in traces. We focus on the exhaustive verification problem, which determines whether there is any set of timing and environment conditions under which the circuit may operate incorrectly. We show that the event-swapping properties of DI circuits authorize us to verify exhaustively such circuits by only examining certain special traces.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000

It has been shown earlier that, if we are restricted to unate gate network (UGN) realizations, there exist universal test sets for Boolean functions. Such a test set only depends on the function f , and checks any UGN realization of f for all multiple stuck-at faults and all robustly testable stuck-open faults. In this paper, we prove that these universal test sets are much more powerful than implied by the above results. They also constitute complete delay fault test sets for arbitrary UGN implementations of a given function. This is even true for UGN networks which are not completely testable with respect to the gate or path delay fault model. Our ability to prove the temporal correctness of such circuit realizations comes from the fact that we do not argue the correctness of individual paths, but rather complete path systems.

2010

Nowadays, the digital circuit production is carried out specifying the circuit functionality using a hardware description language. Then, this specification is synthesized down to a structural netlist suitable for use by the target technologys place-and-route applications. Many synthesis tools make this task introducing some unnecessary gates and wires in the final circuit. As a consequence, it can appear a circuit containing one or more paths that do not influence the circuit output. This kind of non-relevant paths is known as False Path. The problem with false paths is that if they are not considered, the circuit delay may be overestimated during design analysis and optimization. For this reason, the digital circuit industry is looking for effective methods and tools to overcome the mentioned drawbacks. This paper presents a system to detect False Paths based on the analysis of the circuit intermediate specification. The tool analyzes the specification using compilation techniques and then applies some special purpose algorithms for detecting false paths. Furthermore, it shows the gates and wires that are not necessary for the circuit final version.