Verification of timed circuits with symbolic delays

2008

Verification of hardware circuits is a fundamental part of the hardware design. The paper presents temporal logic as a very powerful verification tool. Temporal logic is a classical logic perceived as a function of time. Now, the truth values of logical propositions change as the time flows on. We fetch up in a space of logical assertions in which, we emphasize, the time is flowing, that is, it is a variable, not a constant. Temporal logics, in principle, are linear or branching where linear means linear-time temporal logic (LTL) and branching branching-time temporal logic (CTL). Both can be used in SMV (Symbolic Model Verifier), a model checking-based verification system for digital devices. In this paper, we describe the results we obtained in our verification of a design of the binary comparator. K e y w o r d s: temporal logic, automatic verification, model checking, digital design, Symbolic Model Verifier (SMV)

IEEE Journal of Solid-State Circuits, 1996

Abstruct-A complete set of rules is presented for timing verification of domino-style dynamic circuits. These rules include identification of dynamic nodes, generation of accurate timing constraints based on the operating environment of the gate and verification as an enhanced part of a complete timing veacation process. This methodology has been implemented in a new static timing verifier and used to verify microprocessor circuits.

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2003

The major barrier that prevents the application of formal verification to large designs is state explosion. This paper presents a new approach for verification of timed circuits using automatic abstraction. This approach partitions the design into modules, each with constrained complexity. Before verification is applied to each individual module, irrelevant information to the behavior of the selected module is abstracted away. This approach converts a verification problem with big exponential complexity to a set of sub-problems, each with small exponential complexity. Experimental results are promising in that they indicate that our approach has the potential of completing much faster while using less memory than traditional flat analysis.

IEEE Transactions on Computers, 1988

We present an algebraic methodology allowing us to compare switch-level circuits with higher level specifications. Switch-level networks, "user" behaviors, and input constraints are modeled as asynchronous machines. The model is based on the algebraic theory of characteristic functions (CF). An asynchronous automaton is represented by a pair of CF's, called dynamic CF (DCF): the first CF describes the potential stable states, and the second CF describes the possible transitions. The set of DCF's is a Boolean algebra. Machine composition and internal variables abstraction correspond, respectively, to the product and sum operations of the algebra. Internal variables can be abstracted under the presence of a domain constraint. The constraint is validated by comparison to the outside behavior. The model is well suited for speed-independent circuits for which the specification is given as a collection of properties. Verification reduces to the validation of Boolean inequalities. Index Terms-Abstraction of variables, asynchronous latch, characteristic functions, FIFO queue element, formal verification 3 speed-independent circuit. I. INTRODUCTION ORMAL verification techniques for hardware design are F being developed as an alternative to simulation. Whereas simulation compares results, proofs of correctness involve comparison of functional descriptions. The advantage of formal verification over simulation is that it is a complete method; however, its cost is high computational complexity. Verification must proceed hierarchically, at each level reducing the description complexity by means of abstraction. Numerous theoretical models have been proposed: algebraic methods [27], [16], axiomatic models [23], [25], denotational models using recursive expressions [ 121, [20], predicate logic [I], 1281, [29], and various forms of temporal logic [3], [ll], [211, 1221. The main problem of formal verification are: 1) how to obtain a functional description from the circuit structure, and 2) how to express the high-level specification suitable for comparison. The first problem requires the definition of a formal model, including the specification of primitive elements (axioms), and composition and abstraction laws. Formal verification meth-Manuscript

1995

The verification of real-time properties requires model checking techniques for quantitative temporal structures and real-time temporal logics. However, up to now, most of those problems were solved by a translation into a standard CTL model checking problem with unit-delay structures. Although usual CTL model checkers like SMV can be used then, the translation leads to large structures and CTL formulas, such that the verification requires large computation times and only small circuits can be verified. In this paper a new model checking algorithm for quantitative temporal structures and quantitative temporal logic is presented, which avoids these drawbacks. Motivated by low-level circuit verification, the implemented prover can be used for verifying general real-time systems. Although it has been proved that the complexity of the new algorithm is identical to the corresponding CTL model checking problem, the application of the new algorithms leads to significant better runtimes and larger verifiable structures. The paper presents the underlying algorithms, the complexity proof, implementational issues and concludes with experimental results, demonstrating the advantages of our approach.

1983

Abstract Establishing the correctness of complicated asynchronous circuit is in general quite difficult because of the high degree of nondeterminism that is inherent in such devices. Nevertheless, it is also very important in view of the cost involved in design and testing of circuits. We show how to give specifications for circuits in a branching time temporal logic and how to mechanically verify them using a simple and efficient model checker. We also show how to tackle a large and complex circuit by verifying it hierarchically. f.

Formal Methods in System Design, 2003

This paper presents a novel approach for real-time model checking. It combines the efficiency of traditional symbolic model checking with possibilities to describe and specify real-time systems. Using multi-terminal binary decision diagrams to represent time and time intervals, it becomes possible to transfer efficient algorithms and optimization heuristics known from standard CTL model checking to real-time applications. By introducing a

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), 1999

In this paper, we present a new method for verifying the realizability of a timing diagram with linear timing constraints, thus ensuring that the implementation of the underlying interface is feasible. The method is based on the consistency of the timing constraints derived from the timing diagram and accepts unknown occurrence times for events produced by the environment.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2001

Recent design examples have shown that significant performance gains are realized when circuit designers are allowed to make aggressive timing assumptions. Circuit correctness in these aggressive styles is highly timing dependent and, in industry, they are typically designed by hand. In order to automate the process of designing and verifying timed circuits, algorithms for their synthesis and verification are necessary. This paper presents timed event/level (TEL) structures, a specification formalism for timed circuits that corresponds directly to gate-level circuits. It also presents an algorithm based on partially ordered sets to make the state-space exploration of TEL structures more tractable. The combination of the new specification method and algorithm significantly improves efficiency for gate-level timing verification. Results on a number of circuits, including many from the recently published gigahertz unit Test Site (guTS) processor from IBM indicate that modules of significant size can be verified using a level of abstraction that preserves the interesting timing properties of the circuit. Accurate circuit level verification allows the designer to include less margin in the design, which can lead to increased performance

Electronic Notes in Theoretical Computer Science, 2001

Current approaches for analyzing timed systems are based on an explicit enumeration of the discrete states and thus these techniques are only capable of analyzing systems with a handful of timers and a few thousand states. We address this limitation by describing how to analyze a timed system fully symbolically, i.e., by representing sets of discrete states and their associated timing information implicitly. We demonstrate the e ciency of the symbolic technique by computing the set of reachable states for a non-trivial timed system and compare the results with the state-of-the-art tools Kronos and Uppaal. With an implementation based on difference decision diagrams, the runtimes are several orders of magnitudes better. The key operation in obtaining these results is the ability t o a d v ance time symbolically. We s h o w how to do this e ciently by essentially quantifying out a s p e c i a l v ariable z which is used to represent the constant zero. The symbolic manipulations given in this paper are su cient t o v erify TCTL-formulae fully symbolically.