Noisy random Boolean formulae: A statistical physics perspective

arXiv (Cornell University), 2017

Modern computing systems based on the von Neumann architecture are built from silicon complementary metal oxide semiconductor (CMOS) transistors that need to operate under practically error free conditions with 1 error in 10 15 switching events. The physical dimensions of CMOS transistors have scaled down over the past five decades leading to exponential increases in functional density and energy consumption. Today, the energy and delay reductions from scaling have stagnated, motivating the search for a CMOS replacement. Of these, spintronics offers a path for enhancing the functional density and scaling the energy down to fundamental thermodynamic limits of 100 to 1000. However, spintronic devices exhibit high error rates of 1 in 10 or more when operating at these limits, rendering them incompatible with deterministic nature of the von Neumann architecture. We show that a Shannon-inspired statistical computing framework can be leveraged to design a computer made from such stochastic spintronic logic gates to provide a computational accuracy close to that of a deterministic computer. This extraordinary result allowing a 10 13 fold relaxation in acceptable error rates is obtained by engineering the error distribution coupled with statistical error compensation.

2010

A short survey is provided about our recent explorations of the young topic of noisebased logic. After outlining the motivation behind noise-based computation schemes, we present a short summary of our ongoing efforts in the introduction, development and design of several noise-based deterministic multivalued logic schemes and elements. In particular, we describe classical, instantaneous, continuum, spike and random-telegraphsignal based schemes with applications such as circuits that emulate the brain's functioning and string verification via a slow communication channel.

2006

As CMOS devices and operating voltages are scaled down, noise and defective devices will impact the reliability of digital circuits. Probabilistic computing compatible with CMOS offers a possible solution. In this work, we present a new area and power efficient design methodology for the implementation of a probabilistic framework into CMOS technology based on Markov Random Fields (MRF). Using SPICE, we simulate elementary logic components and sample circuits from the MCNC'91 benchmark set and show the area and power benefits compared to older MRF mapping strategies. We also extend our area and power efficient approach to improving the design of a Hamming decoder based on MRF principles.

2011

We briefly introduce noise-based logic. After describing the main motivations we outline classical, instantaneous (squeezed and non-squeezed), continuum, spike and random-telegraph-signal based schemes with applications such as circuits that emulate the brain functioning and string verification via a slow communication channel.

2010

Current trend of downscaling CMOS transistor dimensions is increasing the liability of digital circuits to be easily affected by noise. The resulting unexpected behaviour of our digital devices is due to the low supply voltage of these downscaled circuit elements. Though the low supply voltage decreases the power dissipation of a circuit to a great extent, it decreases the signal to noise ratio as well. The need to transform the conventional logic gates into modified ones having the same functionality but are highly noise-tolerant is catered by the technique Markov Random Field (MRF) modelling proposed in [1]. This paper contributes towards explaining MRF design in a simplified form, proves the error tolerant capability of MRF circuits by simulations performed in Cadence (simulation software) and finally proposes an improvement in the design of [1].

Journal of Statistical Mechanics: Theory and Experiment, 2011

Random instances of feedforward Boolean circuits are studied both analytically and numerically. Evaluating these circuits is known to be a P-complete problem and thus, in the worst case, believed to be impossible to perform, even given a massively parallel computer, in time much less than the depth of the circuit. Nonetheless, it is found that for some ensembles of random circuits, saturation to a fixed truth value occurs rapidly so that evaluation of the circuit can be accomplished in much less parallel time than the depth of the circuit. For other ensembles saturation does not occur and circuit evaluation is apparently hard. In particular, for some random circuits composed of connectives with five or more inputs, the number of true outputs at each level is a chaotic sequence. Finally, while the average case complexity depends on the choice of ensemble, it is shown that for all ensembles it is possible to simultaneously construct a typical circuit together with its solution in polylogarithmic parallel time.

2011

Probabilistic AND/EXOR networks have been defined, in the past, as a class of Reed-Muller circuits, which operate on random signals. In contemporary logic network design, it is classified as behavioral notation of probabilistic logic gates and networks. In this paper, we introduce additional notations of probabilistic AND/EXOR networks: belief propagation, stochastic, decision diagram, neuromorphic models, and Markov random field model. Probabilistic logic networks, and, in particular, probabilistic AND/EXOR networks, known as turbo-decoders (used in cell phones and iPhone) are in demand in the coding theory. Another example is intelligent decision support in banking and security applications. We argue that there are two types of probabilistic networks: traditional logic networks assuming random signals, and belief propagation networks. We propose the taxonomy for this design, and provide the results of experimental study. In addition, we show that in forthcoming technologies, in particular, molecular electronics, probabilistic computing is the platform for developing the devices and systems for low-power low-precise data processing.

Proceedings of the Design Automation & Test in Europe Conference, 2006

In this paper we present a method which allows the statistical analysis of nanoelectronic Boolean networks with respect to timing uncertainty and noise. All signals are considered to be instationary random processes which is the most general signal representation. As one cannot deal with random processes per se, we focus on certain statistical properties which are propagated through networks of Boolean gates yielding the instationary probability density function (pdf) of each signal in the network. Finally, several values of interest as the error probability, the average path delay or the average signal trace over time can be extracted from these pdf.

It is known that ǫ-noisy gates with 2 inputs are universal for arbitrary computation (i.e. can compute any function with bounded error), if all gates fail independently with probability ǫ and ǫ < β 2 = (3 − √ 7)/4 ≈ 8.856%. In this paper it is shown that this bound is tight for formulas, by proving that gates with 2 inputs, in which each gate fails with probability at least β 2 cannot be universal. Hence, there is a threshold on the tolerable noise for formulas with 2-input gates and it is β 2. It is conjectured that the same threshold also holds for circuits. Index Terms-Computation with unreliable components, fault-tolerant computation, noise threshold √ 7 4. Second, they show that with NAND-gates alone this bound cannot be improved (They make some additional assumptions which we discuss below). This left open the question of what the bound is if we allow all 16 gates with fan-in 2. We settle this question in this paper.

2003

As current silicon-based techniques fast approach their practical limits, the investigation of nanoscale electronics, devices and system architectures becomes a central research priority. It is expected that nanoarchitectures will confront devices and interconnections with high inherent defect rates, which motivates the search for new architectural paradigms. In this paper, we propose a probabilistic-based design methodology for designing nanoscale computer architectures based on Markov Random Fields (MRF). The MRF can express arbitrary logic circuits and logic operation is achieved by maximizing the probability of state configurations in the logic network. Maximizing state probability is equivalent to minimizing a form of energy that depends on neighboring nodes in the network. Once we develop a library of elementary logic components, we can link them together to build desired architectures based on the belief propagation algorithm. Belief propagation is a way of organizing the global computation of marginal belief in terms of smaller local computations. We will illustrate the proposed design methodology with some elementary logic examples.