Papers by Matteo SONZA REORDA
Journal of Electronic Testing
Continuous advances of microelectronics technology have allowed a continued increase of integrati... more Continuous advances of microelectronics technology have allowed a continued increase of integration density and operating frequency. However, this is making the integrated circuits more susceptible to noise and environmental conditions (e.g., radiations, temperature, etc.). Process parameter variations are also on the rise. Consequently, it is becoming increasingly more difficult to guarantee that a fabricated chip will operate correctly after manufacture and in the field. This dramatic trend is accompanied by an increasing demand for high reliability, availability and serviceability (RAS) from significant portions of the electronics markets. How to guarantee that the advances allowed by the continuous development of microelectronics technology will not result in decreased RAS and a consequent dissatisfaction of the electronics markets remains an open question. The adoption of on-line testing techniques can be a solution. Innovative strategies in this direction are presented throughout this special issue, which contains nine papers whose preliminary versions were presented at the IEEE International On-Line Testing Symposium. New techniques for designing checkers for t-UED and BUED codes are presented in a paper by Tarnick. The problem of the design of analog checkers is addressed in the paper by Stratigopoulos and Makris. Due to their widespread adoption the issue of implementing parity prediction functions in FPGAs is becoming crucial and this is addressed in the paper by Ko and Lo. Transient faults affecting combinational components are of current concern. The paper by Omaña, Rossi and Metra proposes new techniques for modeling them. In another paper, Sonza Reorda and Violante describe a new technique to efficiently analyze their effects. The paper by Matakias, Tsiatouhas, Arapoyanni and Haniotakis introduces a new circuit that concurrently detects soft and timing errors. In the next paper, Nieuwland and Kleihorst report theoretical and experimental work on the challenging issue of evaluating the impact on the costs of an integrated circuit stemming from the adoption of fault tolerant design solutions. A new technique for transient current testing evaluation is proposed in the paper by Alorda and Segura, and the paper by Rajabzadeh, Miremadi and Mohandespour provides hints on how to enhance the error detection capabilities of a microprocessor. We hope that the readers will find the articles of this special issue to be interesting. We would like to thank the editor-in-chief, authors and reviewers for making this issue possible.
High Quality Test Pattern Generation for RT-level VHDL Descriptions
In current microprocessor design, an increasingly high silicon portion is derived through automat... more In current microprocessor design, an increasingly high silicon portion is derived through automatic syn- thesis. Effective test generation procedures working on the HDL before synthesis would therefore be extremely useful to shorten the design cycle and increase the test quality. This paper presents an effective test pattern generator working at the RT-level on the synthesizable VHDL source. The tool is
System-level Test and Validation of Hardware/Software Systems
Springer Series in Advanced Microelectronics, 2005
Modeling Permanent Faults.- Test Generation: A Symbolic Approach.- Test Generation: A Heuristic A... more Modeling Permanent Faults.- Test Generation: A Symbolic Approach.- Test Generation: A Heuristic Approach.- Test Generation: A Hierarchical Approach.- Test Program Generation from High-level Microprocessor Descriptions.- Tackling Concurrency and Timing Problems.- An Approach to System-level Design for Test.- System-level Dependability Analysis.
IEEE Transactions on Computers, 2006
Hardening SoCs against transient faults requires new techniques able to combine high fault detect... more Hardening SoCs against transient faults requires new techniques able to combine high fault detection capabilities with the usual requirements of SoC design flow, e.g., reduced design-time, low area overhead, and reduced (or null) accessibility to source core descriptions. This paper proposes a new hybrid approach which combines hardening software transformations with the introduction of an Infrastructure IP with reduced memory and performance overheads. The proposed approach targets faults affecting the memory elements storing both the code and the data, independently of their location (inside or outside the processor). Extensive experimental results, including comparisons with previous approaches, are reported, which allow practically evaluating the characteristics of the method in terms of fault detection capabilities and area, memory, and performance overheads.
A genetic algorithm for automatic generation of test logic for digital circuits
Proceedings Eighth IEEE International Conference on Tools with Artificial Intelligence
ABSTRACT
Within the design arena of modern devices based on cutting-edge processor cores, the availability... more Within the design arena of modern devices based on cutting-edge processor cores, the availability of effective verification, validation and test methodologies able to work on high-level descriptions of processor cores represents an interesting advantage, since it can dramatically reduce the overall time for design and manufacturing, while improving yield and quality. In this paper we propose a semi-automatic test program generation technique able to target modules in modern computer architectures that implement the multithreading paradigm. The methodology starts from high level descriptions of processor cores and using an incremental multi-run approach produces, with very limited manual intervention, a test set able to maximize verification metrics. Experimental results gathered on a couple of real complex designs (the OpenSPARC™ T1 and T2) show the effectiveness of the proposed methodology.
On the transformation of manufacturing test sets into on-line test sets for microprocessors
20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)
In software-based self-test (SBST), a microprocessor executes a set of test programs devised for ... more In software-based self-test (SBST), a microprocessor executes a set of test programs devised for detecting the highest possible percentage of faults. The main advantages of this approach are its high defect fault coverage (being performed at-speed) and the reduced cost (since it does not require any change in the processor hardware). SBST can also be used for online test of
Improved techniques for multiple stuck-at fault analysis using single stuck-at fault test sets
[Proceedings] 1992 IEEE International Symposium on Circuits and Systems
ABSTRACT
An experimental evaluation of the effectiveness of automatic rule-based transformations for safety-critical applications
Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Over the last years, an increasing number of safety-critical tasks have been demanded to computer... more Over the last years, an increasing number of safety-critical tasks have been demanded to computer systems. In particular, safety-critical computer-based applications are hitting markets where costs is a major issue, and thus solutions are required which conjugate fault tolerance with low costs. In this paper, a software-based app roach for developing safety- critical applications is analyzed. By exploiting an ad-hoc
The continuous technology scaling makes soft errors a critical issue in deep sub-micron technolog... more The continuous technology scaling makes soft errors a critical issue in deep sub-micron technologies, and techniques for assessing their impact are strongly required that combine efficiency and accuracy. FPGA-based emulation is a promising solution to tackle this problem when large circuits are considered, provided that suitable techniques are available to support time-accurate simulations via emulation. This paper presents a novel technique that embeds time-related information in the topology of the analyzed circuit, allowing evaluating the effects of the soft errors known as single event transients (SETs) in large circuits via FPGA-based emulation. The analysis of complex designs becomes thus possible at a very limited cost in terms of CPU time, as showed by the case study described in the paper.
A P1500 compliant architecture for BIST-based Diagnosis of embedded RAMs
Asian Test Symposium, 2001
Analysis of root causes of alpha sensitivity variations on microprocessors manufactured using different cell layouts
2010 IEEE 16th International On-Line Testing Symposium, 2010
... luigi.dilillo}@lirmm.fr 2Politecnico di Torino, Dipartimento di Automatica e Informatica, Tor... more ... luigi.dilillo}@lirmm.fr 2Politecnico di Torino, Dipartimento di Automatica e Informatica, Torino, Italy {michelangelo.grosso, matteo.sonzareorda}@polito ... Section 2 reviews the basic concepts about radiation effects on embedded microprocessors, provides a quick overview on the ...
An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains
22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Page 1. An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST... more Page 1. An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains J. Lagos-Benites Departamento de Ingeniería - SEE Pontificia Universidad Católica del Perú, Lima, Perú lagos.jl@pucp.edu.pe ...
A software-based self-test methodology for system peripherals
2010 15th IEEE European Test Symposium, 2010
Software-based self-test strategies have been mainly proposed to tackle microprocessor testing is... more Software-based self-test strategies have been mainly proposed to tackle microprocessor testing issues, but may also be applied to peripheral testing. However, testing highly embedded peripherals (e.g., DMA or Interrupt controllers) is a challenging task, since their observability and controllability are even more reduced compared to microprocessors and to peripherals devoted to I/O communication (e.g., serial or parallel ports). In this
Lecture Notes in Computer Science, 1999
This paper describes a new approximate approach for checking the correctness of the implementatio... more This paper describes a new approximate approach for checking the correctness of the implementation of a protocol interface, comparing its lowlevel implementation with its high-level prototype. The possibility to validate protocol interfaces is extremely useful in many industrial design flows and the proposed methodology does not impose particular requirements and it is able to fit in existing design flows: the proposed approach is based on coupling a commercial simulator with a genetic algorithm that tries to disprove the equivalence of an implementation with its high-level prototype. The use of a commercial simulator guarantees a complete compatibility with current standards and the method is able to fit painlessly in an existing industrial flow. Moreover, the use of a genetic algorithm allows the analysis of large and realistic designs. Experimental results show that the proposed method is effectively able to deal with realistic designs, discovering potential problems, and, although approximate in nature, it is able to provide a high degree of confidence in the results.
IFIP Advances in Information and Communication Technology, 2013
Software-Based Self-Test (SBST) approaches have shown to be an effective solution to detect perma... more Software-Based Self-Test (SBST) approaches have shown to be an effective solution to detect permanent faults, both at the end of the production process, and during the operational phase. However, when Very Long Instruction Word (VLIW) processors are addressed these techniques require some optimization steps in order to properly exploit the parallelism intrinsic in these architectures. In this chapter we present a new method that, starting from previously known algorithms, automatically generates an effective test program able to still reach high fault coverage on the VLIW processor under test, while minimizing the test duration and the test code size. Moreover, using this method, a set of small SBST programs can be generated aimed at the diagnosis of the VLIW processor. Experimental results gathered on a case study show the effectiveness of the proposed approach.
An Exact and Efficient Critical Path Tracing Algorithm
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications, 2010
... e Informatica Politecnico di Torino Corso Duca degli Abruzzi 25, Torino, Italy e-mail: {paolo... more ... e Informatica Politecnico di Torino Corso Duca degli Abruzzi 25, Torino, Italy e-mail: {paolo.bernardi@polito.it, matteo.sonzareorda@polito.it} ... masking occurs when the fault effect, propagated along two or more paths, reconverges with opposite parities at a gate Gi and blocks ...
Proceedings -Design, Automation and Test in Europe, DATE '05, 2005
Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. Howev... more Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected by TMR running on programmable platforms is to prevent upsets in the routing from provoking undesirable connections between signals from distinct redundant logic parts, which can generate an error in the output. This paper investigates the optimal design of the TMR logic (e.g., by cleverly inserting voters) to ensure robustness. Four different versions of a TMR digital filter were analyzed by fault injection. Faults were randomly inserted straight into the bitstream of the FPGA. The experimental results presented in this paper demonstrate that the number and placement of voters in the TMR design can directly affect the fault tolerance, ranging from 4.03% to 0.98% the number of upsets in the routing able to cause an error in the TMR circuit.
On the automation of the test flow of complex SoCs
Modern systems-on-chip (SoCs) allow integrating many different functional cores in the same piece... more Modern systems-on-chip (SoCs) allow integrating many different functional cores in the same piece of silicon. Their test requires taking fast decisions in the selection of structures and strategies at different stages of the design flow: early computation of area overhead, power consumption and test application time are indispensable in order to develop effective and efficient test for the overall chip,
Embedded memory diagnosis: An industrial workflow
Embedded memory modules are sensitive components that deeply influence production yield of integr... more Embedded memory modules are sensitive components that deeply influence production yield of integrated devices. For fast yield improvement, an efficient manufacturing test must supply advanced defect characterization that helps in discovering technology weaknesses and finding strategies for improvement. This paper presents an industrial workflow for embedded memory diagnosis. It is based on the integration of March-based diagnostic BIST hardware in
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Papers by Matteo SONZA REORDA