MPEG-2 Motion Estimation using a PC Cluster

In order to increase transmission efficiency of the real world video sequences, Motion estimation (2) plays an vital role. An improved version of the reconfigurable block motion estimation algorithm (3) is proposed in this paper. The new algorithm uses a small cross-shaped search patterns to speed up the motion estimation of stationary and quasi- stationary blocks. Also we propose a pipelining method for SAD unit to minimize clock delays with minimum area overhead. Our approach increases speed and enhance the throughput for Codec design. We propose a new method “Block Motions matching technique (BMM)” (2) where compression takes place at both Spatial and Temporal domain. In BMM, images are sub divided into micro blocks of 16x16 matrices and it is checked with nearby blocks. Also this method is applied for video compression techniques. The advantage of BMM over existing system is that it compresses block level compression instead of pixel level compression that improves execution speed and adapt for fast processing.

1997

Block matching motion estimation accounts for a high computational overhead inmost low bit-rate video coders intended for video-conferencing and multimedia applications.Conventional fixed size block matching (FSBM) and more sophisticatedvariable size block matching (VSBM) algorithms are profiled to determine how parallelismcan be applied to increase efficiency. Three parallel implementations areconsidered: a homogeneous workstation network using PVM; a Parsytec SuperCluster,128-node T800...

2011

Now a day, MPEG-4 is the most apparent multimedia standard which combines natural interactivity, synthetic digital videos and computer graphics. It has a wide variety of applications such as video conferencing, computer games and mobile phones etc. All the applications need portable video communicators, so low power VLSI implementations are required. In addition to the required portable devices, a care must be taken for the band width limitations. To perform an effective transmission of video sequences using the limited Bandwidth, the input data must be compressed and coded to fit these limited resources .This paper aims towards the realization of an efficient estimation of moving components in a video image sequences to isolate moving image from the static background. The architecture developed in this paper uses LMS algorithm for estimating the noise components and also uses Block Matching Algorithm for the detection of moving components in the frame sequences. Further Huffman dec...

2011 First International Conference on Data Compression, Communications and Processing, 2011

Block matching algorithms (BMA) are central to optimal frame prediction for motion estimation in video compression. This paper focuses on the efficiency of Hierarchical Search (HS) algorithms. The research proposed two new combinations of fast algorithms like Small Diamondshaped Search Pattern (SDSP) and Square-Shaped Search Pattern (SSSP) with a three-level Hierarchical algorithm at different levels of hierarchy. The computational complexity and efficiency for each combination algorithm were of interest. Simulation results show that the hierarchical combination algorithms are around 10% faster than the classic hierarchical algorithm with slight improvement or no significant change in video quality when compared to general HS algorithm.

-In the newest high efficiency video coding (HEVC) standard, the motion estimation (ME) takes around 70% of the encoding time in HM encoder. In order to reduce the complexity of the ME module in HEVC, this paper proposes a flexible coding tree unit (CTU)-level parallel ME method using a graphics processing unit (GPU). The proposed method can be combined with fast CTU-level multiple reference frame motion estimation (MRF-ME) to further reduce the encoding time. Firstly, we decompose ME algorithm into three kernels to achieve a highly parallel computation with a low external memory on GPU. Secondly, the kernel 1 executes a GPU program of calculating the sum of absolute differences (SAD) of small coding unit (SCU 88). Thirdly, the kernel 2 merges the variable block size from SCU (88) to large coding unit (LCU 6464). Finally, the kernel 3 compares minimum SAD to find the best matching block. Simulation results show that the proposed method can achieve an average time improving ratio of MRF-ME module about 96.68% and 97.78% when compared to HM16.7 under MRF=4 and MRF=8, respectively.

International Journal of Electrical and Computer Engineering (IJECE), 2017

Block matching algorithm (BMA) for motion estimation (ME) is the heart to many motion-compensated video-coding techniques/standards, such as ISO MPEG-1/2/4 and ITU-T H.261/262/263/264/265, to reduce the temporal redundancy between different frames. During the last three decades, hundreds of fast block matching algorithms have been proposed. The shape and size of search patterns in motion estimation will influence more on the searching speed and quality of performance. This article provides an overview of the famous block matching algorithms and compares their computational complexity and motion prediction quality. 1. INTRODUCTION The main objective of block matching algorithms is to determine the direction and magnitude of motion (motion vector) for a macroblock in the current frame relative to the best matched candidate block in the reference frame. The search for the best matching candidate block may be carried out by comparing the macroblock in the current frame with some or all the possible candidate blocks in a search window. Full-Search (FS) is an exhaustive search algorithm and it is the simplest method to find the optimal motion vectors for each macroblock. It determines the best matched candidate block through calculating the Sum of Absolute Difference (SAD) for all candidate blocks in the search window. Although Full-Search can obtain the global optimal result, it has very intensive computations. To reduce the complexity of Full-Search, several fast search motion estimation algorithms have been proposed at the price of slightly impaired Peak Signal-to-Noise Ratio (PSNR) performance. A possible classification of these fast search motion estimation algorithms into the following categories: reduction in search positions [1-9], predictive search [10-14], search pattern switching [15], [16], multi-resolution search [17-20] and Fractional-Pixel Interpolation [21-22]. Existing fast search motion estimation algorithms use one or a combination of these categories. A popular example is the three-step search (TSS) algorithm [1]. However, its uniformly spaced search pattern is not well matched to most real-world video sequences in which the motion vector distribution is non-uniformly biased toward the zero vector. Such an observation inspired the new three-step search (NTSS) which has a centre-biased search pattern and supports a halfway-stop technique [2]. The centre-biased NTSS algorithm is an improved version of TSS, tends to achieve much superior performance with fewer number of search points on average. The search pattern has an important influence on speed and distortion performance in block motion estimation. In TSS and NTSS algorithms square-shaped search patterns of different sizes are employed. The Diamond search (DS) algorithm adopts a diamond-shaped search pattern [3], which is more efficient than

ACM Transactions on Design Automation of Electronic Systems, 2019

Variable block size motion estimation has contributed greatly to achieving an optimal interframe encoding, but involves high computational complexity and huge memory access, which is the most critical bottleneck in ultra-high-definition video encoding. This article presents a hardware-efficient block matching algorithm with an efficient hardware design that is able to reduce the computational complexity of motion estimation while providing a sustained and steady coding performance for high-quality video encoding. A three-level memory organization is proposed to reduce memory bandwidth requirement while supporting a predictive common search window. By applying multiple search strategies and early termination, the proposed design provides 1.8 to 3.7 times higher hardware efficiency than other works. Furthermore, on-chip memory has been reduced by 96.5% and off-chip bandwidth requirement has been reduced by 39.4% thanks to the proposed three-level memory organization. The corresponding power consumption is only 198mW at the highest working frequency of 500MHz. The proposed design is attractive for high-quality video encoding in real-time applications with low power consumption.

… and Interpretation, 2008. SSIAI 2008. IEEE …, 2008

Video compression requires high level of computation complexity at every stage especially motion estimation. Recent studies showed the motion estimation module consumes 97% of over all resources. Therefore, it is essential to embed these complex computationally intensive ...

2006 IEEE Workshop on Multimedia Signal Processing, 2006

This paper presents a new H.264 motion estimation algorithm and architecture for video encoding. The algorithm resolves the sequential data dependencies of H.264 motion estimation by a new method, called "Staggered Approach". It adapts existing motion search methods (3DRS, hierarchical full search), maximizing parallel execution and allowing efficient pipelined execution while maintaining the high compression rate of H.264. Its regular and reduced-computation processing scheme makes the algorithm particularly suitable for highperformance hardware implementations, as required for realtime encoding of HDTV. The proposed motion estimator architecture demonstrates the suitability of the algorithm for cost-efficient consumer HDTV encoder chips.

Journal of Balkan Libraries Union, 2017

Humanity created different methods for sharing information. One of the first forms of sharing information and knowledge were images. In the beginning, the process of sharing was relying on static appearances. With the invention of moving pictures by Eadweard Muybridge in the first part of 1870s, this exchange and sharing gained a new quality. Now it was possible to show and preserve motion too. Since that time, technology has changed rapidly. The latest discoveries and improvements from the point of view of technology use computer and IT technologies extensively. Today it is possible for everybody to create and record movies by themselves using affordable and convenient technological devices. Also the process of sharing evolved rapidly and become cheaper and cheaper. We are now able to record some movies and share them through the Internet or other carriers in real time or near real time. However, this also creates serious problems due to the huge volume of data to be sent through the data lines. Therefore, research has concentrated on methods to decrease the data volume without losing the quality. One way to do that is to create effective CODECs. A major drawback of moving pictures is the motion itself. CODECs have to minimize the size of videos without paying the price of quality losses but have also to reduce the computational complexity. Both of these requirements can be achieved with a solid knowledge of motion estimation among others. This paper gives a general overview and survey of some existing and important approaches without the claim of having a complete overview of the field.