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Outline

VLSI Implementation of LDPC Codes

Abstract
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This research focuses on the implementation of Low-Density Parity-Check (LDPC) codes for coded modulation within a Binary Phase Shift Keying (BPSK) system in an Additive White Gaussian Noise (AWGN) environment. It examines the encoder and decoder components of the LDPC system, analyzing the performance based on various parity matrix characteristics such as rate, girth, size, and regularity. The study aims to implement the LDPC code on an FPGA, utilizing a shift-register based design to enhance efficiency while employing a Modified Sum Product (MSP) algorithm for decoding. Performance comparisons are made between theoretical LDPC systems and those implemented on FPGA, focusing on Signal-to-Noise Ratio (SNR) performance.

References (23)

  1. R. Gallagar "Low Density Parity Check Code" IRE Transaction paper Theory pp 21-28, Jan 1962.
  2. R.M.Tanner "A recursive approach to Low complexity codes" IEEE Trans. Information Theory, pp. 533-547 Sept 1981.
  3. D. MacKay and R.Neal "Good codes based on very sparse matrices" in Cryptography and Coding,5 th IMA Conf Springer 1995.
  4. D. MacKay "Good error correcting codes based on very sparse matrices" IEEE Trans. Information Theory ,pp. 399-431,March 1999.
  5. N.Alon and M. Luby "A linear time erasure-resilient code with nearly optimal recovery" IEEE Trans. Inf. Theory ,pp.1732-1736 , Nov 1996
  6. T.J Richardson and R.Urbanke "Efficient encoding of low-density parity-check codes" IEEE Trans. Inf. Theory vol 47 ,pp.638-656 , Feb 2001.
  7. Error detection and correction, http://en.wikipedia.org/wiki/Error_detection_and _correction, July 20, 2010..
  8. M.Luby,M.Mitzenmacher,M.Shokrollahi and D.Spielman "Improved low-density parity check codes using irregular graphs " IEEE Trans. Inf. Theory pp.585-598 , Feb 2001.
  9. J.Bhasker, -A VHDL PRIMER, Prentice-Hall India, Edition 3, 1998.
  10. D.J.C. MacKay http://wol/ra.phy.cam.ac.uk/mackay
  11. C. M. Jorge and G. F. Patrie, Essentials of error-control coding, John Wiley and Sons, Ltd, Chichester, UK, 2006
  12. D. J. C. Mackay, S. T. Wilson and M. C. Davey, "Comparison of construction of irregular Gallager codes", IEEE Transactions on Communications, Vol. 47, pp. 1449-1454, Oct. 1999.
  13. Y. Kou, S. Lin and M. P. C. Fossorier, "Low-density parity-check codes based on finite geometries: a rediscovery and new results", IEEE Transactions on Information Theory, Vol. 47, no. 7, pp. 2711- 2736, Nov. 1981.
  14. Y. Kou, S. Lin and M. P. C. Fossorier, "Low-density parity-check codes based on finite geometries: a rediscovery and new results", IEEE Transactions on Information Theory, Vol. 47, no. 7, pp. 2711- 2736, Nov. 1981.
  15. N. Wiberg, "Codes and Decoding on General Graphs", Ph.D. dissertation, Linkoping University, Sweden, 1996.
  16. S. Myung, K. Yang and J. Kim, "Quasi-cyclic LDPC codes for fast encoding", IEEE Transactions on Information Theory, Vol. 51, no.8, pp. 2894-2900, Aug. 2004.
  17. W. E. Ryan, "An introduction to LDPC codes", Department of Electrical and Computer engineering, University of Arizona, Aug. 2003.
  18. M. P. C. Fossorier, "Quasi-cyclic low-density parity-check codes from circulant permutation matrices", IEEE Transactions on Information Theory, Vol. 50, no. 8, pp. 1788-1794, Aug. 2004
  19. LDPC Code using MATLAB, http://sites.google.com/site/bsnugroho/ldpc
  20. S.Papaharalabos ,P.Sweeney,B.G.Evans, "Modified sum product algorithm for decoding LDPC" ,IET Comm ,2007
  21. William Y .Ryan "An Introduction to LDPC codes" University of Arizona.
  22. Das Shubhashree "FPGA implementation of RS Codes" NIT Rourkela 2011
  23. Hayes David "FPGA implementation of a Flexible LDPC decoder" University of Newcastle