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Low-Density Parity-Check Codes: Construction and Implementation

Profile image of Gabofetswe MalemaGabofetswe Malema

2007

Abstract

Low-Density Parity-Check Codes: Construction and Implementation by Gabofetswe A. Malema Low-density parity-check (LDPC) codes have been shown to have good error correcting performance approaching Shannon's limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost, time, power and bandwidth requirements of target applications. The constructed codes should also meet error rate performance requirements of those applications. Since their rediscovery, there has been much research work on LDPC code construction and implementation. LDPC codes can be designed over a wide space with parameters such as girth, rate and length. There is no unique method of constructing LDPC codes. Existing construction methods are limited in some way in producing good error correcting performing and easily implementable codes for a given rate and length. There is a need to develop methods of constructing codes over a wide range of rates and lengths with good performance and ease of hardware implementability. LDPC code hardware design and implementation depend on the structure of target LDPC code and is also as varied as LDPC matrix designs and constructions. There are several factors to be considered including decoding algorithm computations,processing nodes interconnection network, number of processing nodes, amount of memory, number of quantization bits and decoding delay. All of these issues can be handled in several different ways. This thesis is about construction of LDPC codes and their hardware implementation. LDPC code construction and implementation issues mentioned above are too many to be addressed in one thesis. The main contribution of this thesis is the development of LDPC code construction methods for some classes of structured LDPC codes and techniques for reducing decoding time. We introduce two main methods for constructing structured codes. In the first method, column-weight two LDPC codes are derived from distance graphs. A wide range of girths, rates and lengths are obtained compared to existing

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References (153)

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  2. 5 LDPC Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  3. 5.1 Decoding Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . .
  4. 6 LDPC Code Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  5. 7 LDPC Optimization and Evaluation . . . . . . . . . . . . . . . . . . . . . .
  6. 7.1 LDPC Code Performance Optimization Techniques . . . . . . . . .
  7. 7.2 Error Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  8. 8 LDPC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  9. 9 LDPC Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 3. Constructing LDPC Codes 3.1 Random Constructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  10. MacKay Constructions . . . . . . . . . . . . . . . . . . . . . . . . .
  11. 1.2 Bit-Filling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . .
  12. 1.3 Progressive Edge-Growth Algorithm . . . . . . . . . . . . . . . . .
  13. Structured Constructions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  14. 2.1 Combinatorial Designs . . . . . . . . . . . . . . . . . . . . . . . . .
  15. 2.2 Finite Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  16. 2.3 Algebraic Methods . . . . . . . . . . . . . . . . . . . . . . . . . . .
  17. 2.4 Advantages of Structured Codes . . . . . . . . . . . . . . . . . . . .
  18. 3 Column-Weight Two Codes Based on Distance Graphs . . . . . . . . . . .
  19. 3.1 LDPC Code Graph Representation . . . . . . . . . . . . . . . . . .
  20. 3.2 Cages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  21. 3.3 Code Expansion and Hardware Implementation . . . . . . . . . . .
  22. Performance Simulations . . . . . . . . . . . . . . . . . . . . . . . . Contents
  23. 4 Code Construction Using Search Algorithms . . . . . . . . . . . . . . . . .
  24. 4.1 Proposed Search Algorithm for Structured Codes . . . . . . . . . .
  25. 4.2 Girth-Six Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  26. 4.3 Girth-Eight Codes . . . . . . . . . . . . . . . . . . . . . . . . . . .
  27. Performance Simulations . . . . . . . . . . . . . . . . . . . . . . . .
  28. 5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 4. Constructing Quasi-Cyclic LDPC Codes 4.1 Quasi-Cyclic LDPC Codes . . . . . . . . . . . . . . . . . . . . . . . . . . .
  29. 2 Proposed Search Algorithm for QC-LDPC Codes . . . . . . . . . . . . . .
  30. 3 Column-Weight Two Quasi-Cyclic LDPC Codes . . . . . . . . . . . . . . .
  31. 3.1 Girth-Eight Codes . . . . . . . . . . . . . . . . . . . . . . . . . . .
  32. 3.2 Girth-Twelve Codes . . . . . . . . . . . . . . . . . . . . . . . . . .
  33. 3.3 Girths Higher than Twelve . . . . . . . . . . . . . . . . . . . . . . .
  34. 3.4 Performance Simulations . . . . . . . . . . . . . . . . . . . . . . . .
  35. 4 Quasi-Cyclic Codes of Higher Column-Weights . . . . . . . . . . . . . . . .
  36. 4.1 Girth-Six Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  37. 4.2 Girth-Eight Codes . . . . . . . . . . . . . . . . . . . . . . . . . . .
  38. 4.3 Girth-Ten and Twelve Codes . . . . . . . . . . . . . . . . . . . . . .
  39. 4.4 Performance Simulations . . . . . . . . . . . . . . . . . . . . . . . .
  40. 5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 5. LDPC Hardware Implementation 5.1 LDPC Decoder Architecture Overview . . . . . . . . . . . . . . . . . . . .
  41. 1.1 Number of Processing Nodes . . . . . . . . . . . . . . . . . . . . . .
  42. 1.2 Reduced Hardware Complexity . . . . . . . . . . . . . . . . . . . .
  43. Numeric Precision . . . . . . . . . . . . . . . . . . . . . . . . . . .
  44. 2 Encoder Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  45. 3 Fully Parallel and Random LDPC Decoders . . . . . . . . . . . . . . . . .
  46. 3.1 Structuring Random Codes for Hardware Implementation . . . . . .
  47. 4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 6. Quasi-Cyclic LDPC Decoder Architectures 6.1 Interconnection Networks for QC-LDPC Decoders . . . . . . . . . . . . . .
  48. Hardwired Interconnect . . . . . . . . . . . . . . . . . . . . . . . .
  49. 1.2 Memory Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  50. 2 LDPC Communication through Multistage Networks . . . . . . . . . . . .
  51. 2.1 LDPC Communication . . . . . . . . . . . . . . . . . . . . . . . . .
  52. 2.2 Multistage Networks . . . . . . . . . . . . . . . . . . . . . . . . . .
  53. 2.3 Banyan Network . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  54. 2.4 Benes network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  55. 2.5 Vector Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  56. 3 Message Overlapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  57. 3.1 Matrix Permutation . . . . . . . . . . . . . . . . . . . . . . . . . .
  58. 3.2 Matrix Space Restriction . . . . . . . . . . . . . . . . . . . . . . .
  59. 3.3 Sub-Matrix Row-Column Scheduling . . . . . . . . . . . . . . . .
  60. Proposed Decoder Architecture . . . . . . . . . . . . . . . . . . . . . . . .
  61. 5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 7. Conclusions and Future Work 7.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  62. 2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Publications
  63. G. Malema and M. Liebelt,"Quasi-Cyclic LDPC Codes of Column-Weight Two using a Search Algorithm", European Journal of Advances in Signal Processing,Volume 2007,Article ID 45768, 8 pages,2007.
  64. G. Malema and M. Liebelt,"High Girth Column-Weight Two LDPC Codes based on Distance Graphs", European Journal of Wireless Communications and Network- ing,Volume 2007,Article ID 48158, 5 pages,2007.
  65. G. Malema and M. Liebelt,"Very Large Girth Column-weight two Quasi-Cyclic LDPC Codes", International Conference on Signal Processing,pp.1776-1779,Guilin, China,Nov,2006.
  66. G. Malema and M. Liebelt,"Interconnection network for strcutured Low-Density Parity-Check Decoders", Asia Pacific Communications Conference",pp.537-540,Perth, Australia,October,2005.
  67. G.Malema, M. Liebelt and C.C. Lim," Reduced routing in fully-parallel LDPC de- coders", SPIE: International Symposium on Microelectronics, MEMS, and Nan- otechnology,Brisbane, Australia,December 2005.
  68. G.Malema and M. Liebelt," Low-Complexity Regular LDPC codes for Magnetic Storage Devices", Enformatika : International Conference on Signal Processing,vol.7,pp. 269-271,August,2005.
  69. G. Malema and M. Liebelt,"Programmable Low-Density Parity-Check Decoder", In- telligent Signal Processing and Communications Systems,(ISPACS'04),pp.801-804, Nov,2004.
  70. 11 Column formations for column-weight four girth six codes (a) type I con- nections (b) type II connections. . . . . . . . . . . . . . . . . . . . . . . . .
  71. 12 Column formations for a girth eight (64,3,4) code. . . . . . . . . . . . . . .
  72. 13 Column formations graph structure for girth eight codes for (N,3,k) codes.
  73. 3.14 BER performances of obtained codes with 25 iterations. . . . . . . . . . . .
  74. 1 Quasi-cyclic code sub-matrices arrangement (a) with all non-zero sub- matrices (b) with zero sub-matrices. . . . . . . . . . . . . . . . . . . . . . .
  75. 2 Graph representation of a (16,2,4) code with girth eight. . . . . . . . . . .
  76. 3 Matrix representation of a (16,2,4) code with girth eight. . . . . . . . . . .
  77. 4 General structure of QC-LDPC codes using sequential search. . . . . . . .
  78. 5 LDPC graph three-cycle formations with three groups. . . . . . . . . . . .
  79. 6 Formation of smaller cycles than the target girth. . . . . . . . . . . . . . .
  80. 7 (49,2,7) girth-eight code (a) row connections (b) distance graph connec- tions, (7,4) cage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  81. 8 Row connections for a (70,2,7) code with girth eight. . . . . . . . . . . . .
  82. 9 Girth-eight (49,2,7) code using random search. . . . . . . . . . . . . . . . .
  83. 10 Row connections for girth-twelve LDPC codes (a) (60,2,4) code (b) (80,2,4) code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  84. 11 Group row connections forming girth-sixteen LDPC code with row weight of 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  85. 12 BER performance of obtained codes with 35 iterations. . . . . . . . . . . .
  86. 13 BER performance of larger dimension codes compared to graphical codes with 35 iterations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  87. 14 Girth-six (42,3,6) code using sequential searches. . . . . . . . . . . . . . . .
  88. 15 Row-column connections for (a) (42,4,6) and (b) (42,5,6) girth-six quasi- cyclic codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Group shifts increments for girth-six code. . . . . . . . . . . . . . . . . . .
  89. 17 Row-column connections for a (42,3,6) quasi-cyclic girth-six code using a random search. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  90. 18 BER performance curves for (3,6) regular codes with 25 iterations. . . . . .
  91. 19 Simple protograph with derived code graph structure. . . . . . . . . . . . .
  92. 20 QC-LDPC code structures (a) irregular structure (b) regular structure. . .
  93. 21 BER performances of irregular compared to regular codes. . . . . . . . . .
  94. 22 BER performances regular (504,3,6) qc-ldpc code compared to Mackay and PEG codes of the same size. . . . . . . . . . . . . . . . . . . . . . . . . . .
  95. 23 BER performances regular (1008,3,6) qc-ldpc codes compared to Mackay and PEG codes of the same size. . . . . . . . . . . . . . . . . . . . . . . . .
  96. 24 BER performances irregular (504,3,6) qc-ldpc code compared to Mackay and irregular PEG codes of the same size. . . . . . . . . . . . . . . . . . .
  97. 25 BER performances irregular (1008,3,6) qc-ldpc code compared to Mackay and irregular PEG codes of the same size. . . . . . . . . . . . . . . . . . .
  98. 26 BER performances high-rate qc-ldpc code compared to a finite geometry code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  99. 1 Fully parallel LDPC decoder architecture . . . . . . . . . . . . . . . . . . .
  100. 2 Serial LDPC decoder architecture with unidirectional connections. . . . . .
  101. 3 Semi-parallel LDPC decoder architecture with unidirectional connections. .
  102. 4 Rearranged LDPC matrix for reduced encoding. . . . . . . . . . . . . . . .
  103. 5 Shift encoder for quasi-cyclic LDPC codes. . . . . . . . . . . . . . . . . . .
  104. 6 Restricted space for random code matrix. . . . . . . . . . . . . . . . . . . .
  105. 7 Conventional and half-broadcasting node connections. . . . . . . . . . . . .
  106. 8 Unordered and ordered random code matrix space. . . . . . . . . . . . . .
  107. 9 Row-column connections for an 18×36 random code. . . . . . . . . . . . . 5.10 Permuted 18×36 random code. . . . . . . . . . . . . . . . . . . . . . . . .
  108. 11 Column-row ranges for a random (36,3,6) LDPC matrix. . . . . . . . . . .
  109. 12 Unordered random matrix space, with average wire length of 500. . . . . .
  110. 15 Maximum cut is the number of row-ranges crossing a column. . . . . . . .
  111. 16 Number of vertical row-range cuts for columns. . . . . . . . . . . . . . . .
  112. 1 Block diagram of LDPC decoder direct interconnection nodes. . . . . . . .
  113. 2 Sub-matrix configuration for a parity-check matrix. . . . . . . . . . . . . .
  114. 3 Block diagram of LDPC decoder using memory blocks for communication.
  115. 4 Crossbar communication network. . . . . . . . . . . . . . . . . . . . . . . .
  116. 5 Block diagram of a LDPC decoder using multistage networks. . . . . . . .
  117. × 2 switch passes input data to lower or upper output port. . . . . . . .
  118. 7 4x4 and 8x8 banyan networks. . . . . . . . . . . . . . . . . . . . . . . . . .
  119. 8 A 8x8 Benes network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  120. 9 Computation scheduling of check and variable nodes with and without overlapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  121. 10 Plot of gain with respect to the number of iterations when inter-iteration waiting time is zero. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  122. 12 Row-column connections space. . . . . . . . . . . . . . . . . . . . . . . . .
  123. 13 Scheduling by rearranging the matrix (a) original constructed LDPC matrix (b) rearranged LDPC matrix. . . . . . . . . . . . . . . . . . . . . . . . . .
  124. 14 Overlapped processing of the rearranged matrix. . . . . . . . . . . . . . . .
  125. 15 Overlapping by matrix space restriction. . . . . . . . . . . . . . . . . . . .
  126. 16 Quasi-cyclic basis matrix (a) without space restriction (b) with space re- striction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  127. 17 BER performance of restricted and unrestricted qc-ldpc codes. . . . . . . .
  128. 18 Another overlapping by matrix space restriction. . . . . . . . . . . . . . . .
  129. 19 BER performance of restricted and unrestricted qc-ldpc codes using second space restriction (25 iterations). . . . . . . . . . . . . . . . . . . . . . . . .
  130. 20 quasi-cyclic code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  131. 21 Scheduling example of check and variable nodes with overlapping. . . . . .
  132. 22 Calculation of starting addresses for check and variable nodes with over- lapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  133. circle (a) with two points (b) with three points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  134. 24 Gain with varying waiting time and zero or constant inter-iteration waiting time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  135. 25 Waiting times for a quasi-cyclic (1008,3,6) code of example in Figure 4.24.
  136. 26 BER performance of code with constrained shifts compared to code with unconstrained shifts (25 iterations). . . . . . . . . . . . . . . . . . . . . . .
  137. 27 Matrix configuration with matrix space restriction. . . . . . . . . . . . . .
  138. 28 Overlapping Decoder architecture based on matrix permutation and space restriction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  139. 29 Pipelining of reading, processing and writing stages of decoding computa- tions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  140. 30 Overlapping Decoder architecture based on matrix permutation and space restriction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . List of Tables 3.1 Sizes of some known cubic cages with corresponding code sizes, girths and rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  141. 2 Some of known cages graphs with vertex degree higher than three. . . . . .
  142. 3 Column-weight four girth-six minimum group sizes. . . . . . . . . . . . . .
  143. 4 Column-weight three girth-eight minimum group sizes using type II con- nections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  144. 1 Girth-twelve (N, 2, k) code sizes using sequential searches and two row groups.
  145. 2 Girth-twelve (N, 2, k) codes sizes using random searches and two row groups.
  146. 3 Code sizes with girth higher than twelve using sequential searches. . . . . .
  147. 4 girth-six minimum group sizes with a sequential search. . . . . . . . . . . .
  148. 5 (N,3,k) and (N,4,k) girth-eight codes minimum group sizes using sequential search. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
  149. 6 Obtained (N, 3, k) girth-eight LDPC codes sizes using random searches . .
  150. 7 (N,3,k) LDPC codes sizes with girth ten and twelve. . . . . . . . . . . . . .
  151. 1 Results for different parity-check matrix sizes. (original/reordered matrix)
  152. 6.1 Variable to check nodes communication . . . . . . . . . . . . . . . . . . . .
  153. 2 Check to variable nodes communication . . . . . . . . . . . . . . . . . . . .

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