Thermal-Aware 3D IC Placement via Transformation

2012

In this paper, we propose two methods used in 3D IC placement that effectively exploit the die-to-die thermal coupling in the stack. First, TSVs are spread on each die to reduce the local power density and vertically aligned across dies simultaneously to increase thermal conductivity to the heatsink. Second, we move high-power logic cells to the location that has higher conductivity to the heatsink while moving TSVs in the upper dies so that high-power cells are vertically overlapping below the TSVs. These methods are employed in a force-directed 3D placement successfully and outperform several state-of-the-art placers published in recent literature.

2011

Abstract Existing thermal-aware 3D placement methods assume that the temperature of 3D ICs can be optimized by properly distributing the power dissipations, and ignoring the heat conductivity of though-silicon-vias (TSVs). However, our study indicates that this is not exactly correct.

2007 25th International Conference on Computer Design, 2007

One of the biggest challenges in 3D stacked IC design is heat dissipation. Incorporating thermal vias is a promising method for reducing the temperatures of 3D ICs. The bonding styles between device layers impose certain restrictions to where thermal vias may be inserted. This paper presents a whitespace redistribution algorithm that takes bonding style into consideration to improve thermal via placement, which in turn reduces temperature.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013

3-D integrated circuits (3-D ICs) offer performance advantages due to their increased bandwidth and reduced wirelength enabled by through-silicon-via structures (TSVs). Traditionally TSVs have been considered to improve the thermal conductivity in the vertical direction. However, the lateral thermal blockage effect becomes increasingly important for TSV via farms (a cluster of TSV vias used for signal bus connections between layers) because the TSV size and pitch continue to scale in μm range and the metal to insulator ratio becomes smaller. Consequently, dense TSV farms can create lateral thermal blockages in thinned silicon substrate and exacerbate the local hotspots. In this paper, we propose a thermal-aware via farm placement technique for 3-D ICs to minimize lateral heat blockages caused by dense signal bus TSV structures. By incorporating thermal conductivity profile of via farm blocks in the design flow and enabling placement/aspect ratio optimization, the corresponding hotspots can be minimized within the wirelength and area constraints. Index Terms-3-D floorplanning, analysis, modeling, physical design I. Introduction 3-D INTEGRATION offers a number of benefits for future VLSI design [1]-[7], such as 1) higher packing density and smaller footprint; 2) shorter global interconnect due to the short length of through-silicon vias (TSVs) and the flexibility of vertical routing, leading to higher performance and lower power consumption of interconnects [8]; 3) support of heterogenous integration: each single die can have different technologies [9]. Increased interconnectivity is considered a key advantage in improving performance by leveraging the high-bandwidth and low-latency TSV structures [10]. TSVs are essential in implementing interconnectivity across layers in a wide range of 3-D partitioning approaches: from fine-Manuscript

Three Dimensional Integrated Circuit Design, 2010

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000

In this paper, we present a high-quality analytical 3-D placement framework. We propose using a Huber-based local smoothing technique to work with a Helmholtz-based global smoothing technique to handle the nonoverlapping constraints. The experimental results show that this analytical approach is effective for achieving tradeoffs between the wirelength and the through-silicon-via (TSV) number. Compared to the state-ofthe-art 3-D placer ntuplace3d, our placer achieves more than 20% wirelength reduction, on average, with a similar number of TSVs. Furthermore, we extend this analytical 3-D placement framework with thermal awareness. While 2-D thermal-aware placement simply follows uniform power distribution to minimize temperature, we show that the same criterion does not work for 3-D ICs. Instead, we are able to prove that when the TSV area in each bin is proportional to the lumped power consumption of that bin and the bins in all tiers directly above it, the peak temperature is minimized. Based on this criterion, we implement thermal awareness in our analytical 3-D placement framework. Compared with a TSV oblivious method, which only results in an 8% peak temperature reduction, our method reduces the peak temperature by 34%, on average, with slightly less wirelength overhead. These results suggest that considering the thermal effects of TSVs is necessary and effective during the placement stage. Index Terms-3-D integrated circuits, analytical placement, thermal optimization, through-silicon-via (TSV). I. Introduction 3-D INTEGRATED circuit (IC) technologies can offer the potential to significantly improve system performance and power consumption. 3-D IC technologies also provide a flexible way to carry out heterogeneous system-onchip (SoC) design by integrating disparate technologies.

2016 International Conference on Bio-engineering for Smart Technologies (BioSMART), 2016

With 3D NoCs help improve circuit performance, fault tolerance and energy efficiency through the reduction of average wire-length and the increase in communication bandwidth of on-chip wiring, the soaring increase of on-chip temperature remains one of the most challenging obstacles to their commercialization. We present a physical design flow that integrates thermal driven floor-planning with MOEA. The thermal aware floor-planning help reduce the magnitude of hotspots in each layer, in turn, alleviate the negative impact of heat dissipation on chip performance and reliability. The essence of the flow is to analyze the layered thermal map of the chip stack and then apply MOEA operators, which helps to put the power hungry functional units far from each other.3D stacked heterogeneous mesh architecture with 3 layers is used as the baseline for our experimental work. Further another two layers has been added to check the impact of increasing number of layers on the peak temperature of i...

Proceedings of the 1999 international symposium on Physical design - ISPD '99, 1999

In this work we present a standard cell placement tool that aims at reducing hot spots while optimizing traditional design metrics such as area and wire length. By using the superposition principle and the concept of transfer thermal resistance, w e rst convert the temperature differential constraint to its corresponding power distribution constraint. Dealing directly with power distribution avoids time-consuming temperature calculation during placement. The power distribution constraint is then gradually tightened during the placement process to produce improved temperature pro le. Our simulation results show noticeable improvement of thermal distribution over the traditional placement algorithm. The worst case increase in total wire length is less than 3, and we observe no noticeable area increase.

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2009

In this paper, we present a performance and thermal-aware Steiner routing algorithm for three-dimensional (3-D) stacked integrated circuits. Our algorithm consists of two steps: tree construction and tree refinement. Our tree construction algorithm builds a delay-oriented Steiner tree under a given thermal profile. We show that our 3-D tree construction involves minimization of two-variable Elmore delay function. In our tree refinement algorithm, we reposition the through-silicon-vias (TSVs) used in existing Steiner trees while preserving the original routing topology for further thermal optimization under a performance constraint. We employ a novel scheme to relax the initial nonlinear programming formulation to integer linear programming and consider all TSVs from all nets simultaneously. Our tree construction algorithm outperforms the popular 3-D maze routing by 52% in terms of performance at the cost of 15% wirelength and 6% TSV count increase for four-die stacking. In addition, our TSV relocation results in 9% maximum-temperature reduction at no additional area cost. We also provide extensive experimental results, including the following: 1) the wirelength and delay distribution of various types of 3-D interconnects; 2) the impact of TSV RC parasitics on routing and TSV relocation; and 3) the impact of various bonding styles on routing and TSV relocation. Last, we provide results on two-die stacking.

2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2016

With the rapid increment of the power density and the introduction of vertical stack, heat dissipation has become a challenge issue. Thermal-aware placement thereby attracts more and more attentions for 3D IC. Meanwhile, as the keepgoing scaling-down of IC, a huge computation consumption was caused by the large scale span. In this paper, an equivalent anisotropic thermal conductivity model was introduced to low down the computation consumption caused by the huge feature size difference. Correctness of this model was verified and the deviation from a full-scale simulation was less than 20%. By applying this model, thermal distribution of a designed 3D IC with 1566 TSVs and 80504 hot-spots was obtained with the total computation time of about 24 minutes in a regular personal computer.