Prasun Ghosal

Indian Institute of Engineering Science and Technology, Shibpur, Information Technology, Faculty Member

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Papers by Prasun Ghosal

Improved Extended XY On-Chip Routing in Diametrical 2D MEsh NOC

International Journal of VLSI Design & Communication Systems, 2012

. NoC applies networking theory and related methods to on-chip communication and brings out notab... more . NoC applies networking theory and related methods to on-chip communication and brings out notable improvements over conventional bus and crossbar interconnections. NoC offers a great improvement over the issues like scalability, productivity, power efficiency and signal integrity challenges of complex SoC design. In an NoC, the communication among different nodes is achieved by routing packets through a pre-designed network fabric according to some routing algorithm. Therefore, architecture and related routing algorithm play an important role to the improvement of overall performance of an NoC. A Diametrical 2D Mesh routing architecture has the facility of having some additional diagonal links with simple 2D Mesh architecture. In this work, we have proposed a Modified Extended 2D routing algorithm for this architecture, which will ensure that a packet always reaches the destination through the possible shortest path, and the path is always deadlock free.

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Microstructural stability of the (Î± + Î²) solution-treated and quenched near-Î± titanium alloy Ti5.8Al4Sn3.5Zr0.70Nb0.50Mo0.35Si0.06C

It can be stated that the lower the solution-treatment temperature (in the range studied) in the ... more It can be stated that the lower the solution-treatment temperature (in the range studied) in the (Î± + Î²) phase field followed by oil quenching, the lower is the stability of the resulting microstructure when subjected to aging at 973 K even for a very short time for 2 hours. The term stability is understood in terms of increasing size of the silicide particles that were precipitated and also the Î±â phase caused by the partitioning of alloying elements. Thus, the observed insensitivity and slower fatigue crack rates in the stabilized condition with the embrittling phases (silicides and Î±â) in the bimodal microstructures, as opposed to the other investigations, needs further detailed study.

Department of Information Technology Bengal Engineering and Science University, Shibpur Howrah 711103, WB, India

An efficient and optimized recommendation system using social network knowledge base

2014 International Conference on Advances in Electrical Engineering (ICAEE), 2014

With the advent of e-commerce in the current market a large number of companies e.g. Flipkart, eB... more With the advent of e-commerce in the current market a large number of companies e.g. Flipkart, eBay, infibeam, amazon etc. have come up with a huge range of products on a single platform to the users. These products are recommended to the users based on certain parameters related to the user. Moreover, in order to refine the recommendation these e-commerce based websites have started using social networking sites to access information pertaining to the user in order to improve their recommendation. In this paper we present a novel recommendation system for e-commerce websites using social network knowledge base that uses certain parameters provided by users viz. age group, gender, location etc. and based on these criteria best recommendation is provided by our proposed method using Analytical Hierarchy Process, Merge-and-Sort, and Sort-and-Count algorithms within a wrapper to optimize. User preferences are taken from Facebook whereas Flipkart is chosen as the e-commerce website for illustration of our proposed method.

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A Low Latency Scalable 3D NoC Using BFT Topology with Table Based Uniform Routing

2014 IEEE Computer Society Annual Symposium on VLSI, 2014

A Novel Routing Algorithm for On-Chip Communication in NoC on Diametrical 2D Mesh Interconnection Architecture

Advances in Intelligent Systems and Computing, 2013

To meet the design productivity, scalability and signal integrity challenges of next-generation s... more To meet the design productivity, scalability and signal integrity challenges of next-generation system designs, a structured and scalable interconnection architecture, network on chip (NoC), has been proposed recently to solve the complex on-chip communication problem. In an NoC, the communication among different nodes is achieved by routing packets through a pre-designed network fabric according to some architecture rather than wires. In Diametrical 2D Mesh architecture, advantages of routing include smaller network diameter as well as ...

FL2STAR: A novel topology for on-chip routing in NoC with fault tolerance and deadlock prevention

2013 IEEE International Conference on Electronics, Computing and Communication Technologies, 2013

Abstract CMP (Chip Multiprocessor) based architectures have offered a promising solution in tomor... more Abstract CMP (Chip Multiprocessor) based architectures have offered a promising solution in tomorrow&amp;#x27;s high performance computing demands. Topology and routing policy are playing key roles in designing such architectures to develop a NoC (Network-on-Chip). Major influencing design metrics include scalability, modularity, transport latency, parallelism, and, efficient load-balancing (to avoid generation of hot spots). Efficiency of topology as well as good routing policy is again counted in terms of its ability of fault ...

A performance enhancing hybrid locally mesh globally star NoC topology

Proceedings of the 24th edition of the great lakes symposium on VLSI - GLSVLSI '14, 2014

With the rapid increase in the chip density, Network-on-Chip (NoC) is becoming the prevalent arch... more With the rapid increase in the chip density, Network-on-Chip (NoC) is becoming the prevalent architecture for today's complex chip multi processor (CMP) based systems. One of the major challenges of the NoC is to design an enhanced parallel communication centric scalable architecture for the on chip communication. In this paper, a hybrid Mesh based Star topology has been proposed to provide low latency, high throughput and more evenly distributed traffic throughout the network. Simulation results show that a maximum of 62% latency benefit (for size 8 × 8), 55% (for size 8 × 8), and 42% (for size 12 × 12) throughput benefits can be achieved for proposed topology over mesh with a small area overhead.

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Routing in NoC on Diametrical 2D Mesh Architecture

Lecture Notes in Computer Science, 2012

Network-on-Chip (NoC) has proven itself as a viable alternative for the on-chip communication amo... more Network-on-Chip (NoC) has proven itself as a viable alternative for the on-chip communication among processing cores in recent years. In Diametrical 2D Mesh architecture, advantages of routing include smaller network diameter as well as larger bisection width. Again, fast network access requires a well-constructed optimal routing algorithm. Our proposed routing algorithm ensures that the packet will always reach the destination through the shortest path and it is deadlock free.

L2STAR: A Star Type level-2 2D Mesh architecture for NoC

2012 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, 2012

Network topology and related routing policy play an important role to the improvement of overall ... more Network topology and related routing policy play an important role to the improvement of overall performance of an on chip Network (NoC). A structural scalable interconnection architecture may significantly increase the performance of a NoC in terms of scalability, modularity, transport latency, parallelism and all other important metrics. Again, well-constructed network architecture may also balance load of the network and try to reduce the chance of causing a hot spot on the network. In this work, our primary objective was to design an efficient scalable NoC architecture to improve performance of a NoC in all these aspects. In this paper, we present a new architecture, called Star Type level-2 Mesh architecture (L2STAR), which is, very much similar to a Multilevel Mesh and Star Type 2D Mesh NoC architecture. Our proposed architecture reduces the network latency considerably and also tries to balance the load of the network and ensures that the packet will always reach the destination through the possible shortest, deadlock free path.

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A provably good performance centric NoC topology

2013 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2013

ABSTRACT As chip density increases rapidly with every process generation, the use of Network-on-C... more ABSTRACT As chip density increases rapidly with every process generation, the use of Network-on-Chip (NoC) has become the prevalent architecture for SoC, MPSoC, and, large scale CMP (Chip Multi Processor) based designs. Diverse NoC solutions have been proposed by the researchers to meet the enhanced on-chip communication requirements. Here, underlying network interconnection architecture (topology), router design and routing policy play an important role for overall system performance improvement. In this work, a 2D Hybrid Mesh based Star topology has been proposed with an objective of providing low latency, low channel contention and higher throughput based system. The observe experimental results show a maximum latency benefit of 62% and increase of 48% in throughput for this proposed topology compared to simple 2D mesh in cost of additional area overhead.

Network-on-chip routing using Structural Diametrical 2D mesh architecture

2012 Third International Conference on Emerging Applications of Information Technology, 2012

Abstract Performance of a NoC (network-on-chip) strongly depends on its underlying architecture a... more Abstract Performance of a NoC (network-on-chip) strongly depends on its underlying architecture and related routing techniques. A structural scalable interconnection architecture may significantly increase the performance of a NoC in terms of scalability, modularity, transport latency and parallelism in communication. Well-constructed network architecture will also balance load of the network and try to reduce the chance of causing a hot spot on the network. In this work, our primary objective was to design an efficient NoC ...

SD2D: A Novel Routing Architecture for Network-on-Chip

2012 International Symposium on Electronic System Design (ISED), 2012

ABSTRACT Properly structural scalable interconnection architecture may significantly increase the... more ABSTRACT Properly structural scalable interconnection architecture may significantly increase the performance of a Network-on-Chip (NoC) in terms of scalability, modularity, transport latency and parallelism in communication. Well constructed network architecture can also balance load of the network and try to reduce the chance of causing a hot spot on the network. In this work, our primary objective was to design an efficient NoC architecture to increase its performance in all these aspects with distribution of the load across the network as well as trying to reduce the diameter of the network in order to reduce the cost of routing. In this paper, we present a new architecture, called Structural Diametrical 2D (SD2D) mesh based on Structural Diametrical XY deterministic routing algorithm that tries to balance the load of the network, increase the level of parallelism, ensures that the packet will always reach the destination through the possible shortest as well as deadlock free path.

An improved lead wire compensation technique for conventional four wire resistance temperature detectors (RTDs)

Measurement, 2011

A new lead wire compensation technique is presented for conventional four wire resistance tempera... more A new lead wire compensation technique is presented for conventional four wire resistance temperature detectors (RTDs). Existing four wire resistance temperature detectors generally use bridge balance technique to achieve balance and unbalance bridge output is calibrated in terms of unknown temperature. Out of the four leads, two leads are connected to one arm of the bridge while the other two leads are connected to the opposite arm of the bridge, normally known as ratio arms. The presented technique totally nullifies the effect of lead resistances and any temperature variations along the lead wires will not affect the measurement accuracy.

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Diametrical Mesh of Tree (D2D-MoT) Architecture: A Novel Routing Solution for NoC

Abstract—Network-on-chip (NoC) is a new aspect for designing of future System-On-Chips (SoC) wher... more Abstract—Network-on-chip (NoC) is a new aspect for designing of future System-On-Chips (SoC) where a vast number of IP cores are connected through interconnection network. The communication between the nodes occurred by routing packets rather than wires. It supports high degree of scalability, reusability and parallelism in communication. In this paper, we present a Mesh routing architecture, which is called Diametrical 2D Mesh of Tree, based on Mesh-of-Tree (MoT) routing and Diametrical 2D Mesh. It has the advantage of having ...

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Addressing Hardware Security Challenges in Internet of Things: Recent Trends and Possible Solutions

by Subha Koley and Prasun Ghosal

ABSTRACT

An ABCD Parameter-based Modeling and Analysis of Crosstalk Induced Effects in Single-Walled Carbon Nanotube Bundle Interconnects

Single-walled carbon nanotubes (SWCNTs) have the potential to revolutionize the interconnects in ... more Single-walled carbon nanotubes (SWCNTs) have the potential to revolutionize the interconnects in future nanoscale integrated circuits. In the proposed work, crosstalk effects are investigated in SWCNTs at 21 nm and 15 nm technology nodes for intermediate as well as global interconnects. An ABCD parameter based approach has been used to investigate crosstalk delay and noise in both sparse as well as dense SWCNT bundled interconnect system. It is evident from the simulation results that the proposed model is not only 100% accurate but also almost 10 times faster than SPICE. The worst case crosstalk induced delay and peak crosstalk noise voltages for SWCNT bundle interconnects are compared to those of conventional copper (Cu) interconnects at the intermediate as well as global level interconnects. Simulation results also confirm that dense SWCNTs are always ahead of sparse SWCNTs with respect to performance advantage numbers over copper for every levels of interconnects and irrespective of technology nodes. As far as the worst case peak crosstalk noise is concerned, there is a critical length after which the performance of the dense SWCNT bundles is better than that of its sparse counterpart. Proposed model, analysis, along with supportive simulation results prove that dense SWCNT bundled interconnect is one of the most promising alterative interconnect solution for future generation of nanoscale circuits compared to copper with respect to performance as well as signal integrity issues.

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Diametric Mesh of Tree (DiaMoT) Routing Framework for High Performance NoCs: A Hierarchical Approach

2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems, 2012

Abstract Scalability issue is playing a very important role for the highly complex processing sys... more Abstract Scalability issue is playing a very important role for the highly complex processing systems for the future generation of Network-on-Chips (NoCs). A large number of cores are connected to the communication fabric (router based network) using network interfaces inside an NoC. The problem complexity again increases with the increase in numbers of cores and components. Existing solutions can not be easily extended to solve this issue. In this paper, a new multilevel architecture for network on chip (NOC) and its corresponding ...

Performance modeling and analysis of carbon nanotube bundles for future VLSI circuit applications

Journal of Computational Electronics, 2014

ABSTRACT In this work, we have presented a comprehensive analysis of the performance of copper (C... more ABSTRACT In this work, we have presented a comprehensive analysis of the performance of copper (Cu) and existing carbon nano tube (CNT) bundle structures (i.e. SWCNT, DWCNT and MWCNT) across nanometer technology nodes like 45, 32, 22 and 16 nm at local, intermediate and global level interconnects. Double walled carbon nano tubes (DWCNTs) and multi walled carbon nano tubes (MWCNTs) are modeled like simple single walled carbon nano tube (SWCNT) equivalent model with high accuracy. The analytical closed form delay expressions for SWCNT, DWCNT and MWCNT bundles have been found out. It has been observed that sparse SWCNT bundle interconnects show about 50 % performance improvement for 20 m long local level interconnects over Cu in 16 nm technology node, whereas the performance advantage numbers for MWCNT and sparse DWCNT bundles are 50 and 35 % respectively. For 200 m long intermediate level interconnects, the performance advantage numbers are 85, 80 and 75 % for dense SWCNT, MWCNT and dense DWCNT bundles respectively in 16 nm node. For 10 mm long global level interconnects, the performance advantage numbers are 85, 85 and 75 % for dense SWCNT, MWCNT and dense DWCNT bundles respectively in 16 nm node. It is also observed that the performance numbers improve with scaling for all levels of interconnects. It is also shown that the ratio of delay of CNT bundles and Cu for various levels of interconnects agree well with the existing work.

Particle Swarm Optimization of Speed in Unplanned Lane Traffic

by Prasun Ghosal and International Journal of Artificial Intelligence (IJAIA)

Analysis of Speed Optimization Technique in Traffic is a very promising research problem. Searchi... more Analysis of Speed Optimization Technique in Traffic is a very promising research problem. Searching for an efficient optimization method to increase the degree of speed optimization and thereby increasing the traffic flow in a lane is a widely concerning issue. However, there has been a limited research effort on the optimization of the lane usage with speed optimization. This paper presents a novel technique to solve the problem optimally using the knowledge base analysis of speeds of vehicles, population of lanes , using partial modification of Swarm Intelligence which, in turn will act as a guide for design of lanes optimally to provide better optimized traffic with less number of transitions of vehicles between lanes.

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