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Abstract
Introduction
Related Work
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Computer Science
Computer Networks

Hardware-efficient encryption encoder and decoder unit

Profile image of Murali VaranasiMurali Varanasi

2008, MILCOM 2008 - 2008 IEEE Military Communications Conference

https://doi.org/10.1109/MILCOM.2008.4753190
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Abstract

The distribution and retrieval of multimedia data over wireless networks have become widespread, thus creating the need for secure transmission of data over networks. However, one of the main problems with the secure transmission of digital data over wireless networks is that the errors that occur during transmission typically need to be resolved before decryption can begin. Because of the limited resources such as power and size of these wireless devices, hardware-efficient implementations of these operations are essential. This paper presents a joint hardware-efficient design for both encryption and channel coding that is optimized for low-resource requirements. We implemented the Rijndael Advance Encryption Standard (AES) algorithm and convolutional encoder for the encryption and encoder sub-unit, respectively. In order to decode the received digital data, we use the Viterbi decoder, which has been known to be suited for convolutional codes. Our design has a 70% reduction in the number of hardware resources for the encoding sub-unit through the block of XORs. The low-resource usage is achieved through an integrated architecture of the encoding units. Most of the hardware reduction was achieved in the AddRoundKey and the encoder sub-unit. Our system was implemented on a Xilinx Spartan 3 xc3s200FT256 using ISE foundation 8.1, and 13% of the slices were used for the Viterbi decoder with 674 bels. The maximum frequency was 55.872 MHz with a minimum period of 17.898 ns.

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  18. J. B. Sulistyo and D. S. Ha, "A New Characterization Method for Delay and Power Dissipation of Standard Library Cells," VLSI Design, vol. 15, pp. 667-678, 2002.

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