B. Bouallegue

Fac. Sciences Monastir University, Physics, Maitre assistant

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Papers by B. Bouallegue

DWT-AES Processor for a Reconfigurable Secure Image Coding

by B. Bouallegue and Mohsen Machhout

International Journal of Computer Theory and Engineering, 2009

Efficient FPGA Hardware Implementation of Secure Hash Function SHA-2

by Mohsen Machhout, B. Bouallegue, and Hassen Mestiri

International Journal of Computer Network and Information Security, 2014

High performance architecture of integrated protocols for encoded video application

Despite the evolution of high speed communication network to accommodate an increasingly number o... more Despite the evolution of high speed communication network to accommodate an increasingly number of applications with diverse service requirements, there still exist a number of barriers related to the deployment of the encoded video over the ATM network. In fact, additional works have to be devoted to improve protocol architecture and to guarantee the QoS. In this paper, we first analyze the main parameters affecting the visual quality of real video pictures. Then, we define specific services to be implemented at the network interface level. We also discuss the proposed integrated protocols architecture for real time application such as video coding illustrating the function to support the challenges of managing real time services over high speed network. In fact, data cells are exposed to delays and losses, which affect the quality of the video signal. Therefore, we have to perform the adequate processing in order to keep the quality of service on an acceptable level. In this article, we propose the design of an interface between the MPEG-2 standard and the ATM network in order to improve the video visual quality. Our approach tries to overcome the difficulty imposed by traditional random cell discarding due to the bursty aspect of the traffic and the variable bit rate transmission, nature of compressed video. The performance evaluation shows the effectiveness of the proposed interface architecture with the set of mechanisms in improving the robustness of the video delivery system.

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A Reconfigurable Implementation of the New Secure Hash Algorithm

by Mohsen Machhout, B. Bouallegue, and A. Baganne

The Second International Conference on Availability, Reliability and Security (ARES'07), 2007

The main applications of the hash functions are met in the fields of communication's integrity an... more The main applications of the hash functions are met in the fields of communication's integrity and signature authentication. Many hash algorithms have been investigated and developed in the last years. This work is related to hash functions FPGA implementation. Field programmable gate arrays (FPGAs) being reconfigurable, flexible and physically secure are a natural choice for implementation of hash functions in a broad range of applications with different areaperformance requirements. We propose a configurable Secure Hash Algorithm (SHA) processor for extended signature authentication. This paper investigates different optimizations algorithms of recent Techniques that have been proposed in the literature. In our implementation based on Xilinx Virtex FPGAs, the throughput of SHA processor is equal to 1296 Mbit/s. Speed/area results from these processors are analyzed and shown to compare favorably with other FPGAbased implementations. A fastest data throughput is achieved by our optimized algorithm. Second International Conference on Availability, Reliability and Security (ARES'07) 0-7695-2775-2/07 $20.00

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Design and Hardware Implementation of QoSS-AES Processor for Multimedia applications

For real-time applications, there are several factors (time, cost, power) that are moving securit... more For real-time applications, there are several factors (time, cost, power) that are moving security considerations from a function centric perspective into a system architecture (hardware/software) design issue. Advanced Encryption Standard (AES) is used nowadays extensively in many network and multimedia applications to address security issues. The AES algorithm specifies three key sizes: 128, 192 and 256 bits offering different levels of security. To deal with the amount of application and intensive computation given by security mechanisms, we define and develop a QoSS (Quality of Security Service) model for reconfigurable AES processor. QoSS has been designed and implemented to achieve a flexible trade-off between overheads caused by security services and system performance. The proposed architecture can provide up to 12 AES block cipher schemes within a reasonable hardware cost. We envisage a security vector in a fully functional QoSS request to include levels of service for the range of security service and mechanisms. Our unified hardware can run both the original AES algorithm and the extended AES algorithm (QoSS-AES). A novel on-the-fly AES encryption/decryption design is also proposed for 128-, 192-, and 256-bit keys.

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Performance analysis of interleaving for video communications over ATM networks

IEEE International Conference on Systems, Man and Cybernetics, 2002

This paper addresses the importance of interleaving for digital video communication over B-ISDN s... more This paper addresses the importance of interleaving for digital video communication over B-ISDN such as an ATM network. It provides the appropriate solution based on a good knowledge of both the video system interface design and broadband network capabilities. An interface between MPEG-2 and the ATM network architecture is studied to improve the video visual quality. The presented approach tries

Efficient Large Numbers Karatsuba-Ofman Multiplier Designs for Embedded Systems

by B. Bouallegue and Medien Zeghid

Long number multiplications (n ≥ 128-bit) are a primitive in most cryptosystems. They can be perf... more Long number multiplications (n ≥ 128-bit) are a primitive in most cryptosystems. They can be performed better by using Karatsuba-Ofman technique. This algorithm is easy to parallelize on workstation network and on distributed memory, and it's known as the practical method of choice. Multiplying long numbers using Karatsuba-Ofman algorithm is fast but is highly recursive. In this paper, we propose different designs of implementing Karatsuba-Ofman multiplier. A mixture of sequential and combinational system design techniques involving pipelining is applied to our proposed designs. Multiplying large numbers can be adapted flexibly to time, area and power criteria. Computationally and occupation constrained in embedded systems such as: smart cards, mobile phones…, multiplication of finite field elements can be achieved more efficiently. The proposed designs are compared to other existing techniques. Mathematical models (Area (n), Delay (n)) of our proposed designs are also elaborat...

Protocol architecture for MPEG-2 video over a high speed network

IEE Proceedings - Communications, 2004

Real time communication services related to the encoded video transmission over the highspeed net... more Real time communication services related to the encoded video transmission over the highspeed network like ATM need a new integrated protocol architecture to meet the required quality. In fact, data cells are exposed to delays and losses, which affect the video signal quality. So, we have to perform the adequate processing in order to keep the quality of service on an acceptable level. In this article we propose the design of a new adaptation of MPEG-2 video in ATM Networks in order to improve the video visual quality. Our approach, based on a new MPEG-2 protocol architecture, tries to overcome the difficulty imposed by traditional random cell discarding due to the bursty aspect of the traffic and the variable bit rate transmission, nature of encoded video. We demonstrate the importance of including a dynamic bandwidth reallocation and appropriate interleaving technique for a bursty encoded video traffic being carried in ATM Network by comparing the degradation quality of MPEG-2 sequence with and without our proposed techniques. The results show that the proposed interface is effective in solving the cell loss problem and thus enhances the QoS for MPEG-2 video transmission in ATM Networks.

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Design of a priority active queue management

Advances in Computer, …, 2006

... Chang, A. Goel, N. Mckeown, and B. Prabhakar Imatching output queueing with a combined input/... more

Efficient hardware architecture of recursive Karatsuba-Ofman multiplier

by Mohsen Machhout and B. Bouallegue

2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2008

The finite Field multiplication is the basic operation in all cryptographic applications. It can ... more The finite Field multiplication is the basic operation in all cryptographic applications. It can be performed by using Serial, Booth, Montgomery and Karatsuba-Ofman&amp;amp;amp;amp;amp;amp;amp;#x27;s divide-and-conquer technique. The Karatsuba-Ofman multiplier replaces a multiplication by three ones of half-length operands which are performed in parallel. The implementation of Karatsuba-Ofman multiplier has been made both in sequential and parallel architectures. In order to improve

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