Functional Testing of Semiconductor Random Access Memories

Bulletin of Electrical Engineering and Informatics, 2021

Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using very deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist in the memory are described, in terms of their definition and detection requirement. Several memory testing algorithms that are used in memory built-in self-test (BIST) are discussed, in terms of test operation sequences, fault detection ability, and also test complexity. From the studies, it shows that tests with 22 N of complexity such as March SS and March AB are needed to detect all static unlinked or simple faults within the memory cells. The N in the algorithm complexity refers to Nx*Ny*Nz whereby Nx represents the number of rows, Ny represents the number of columns and Nz represents the number of banks. This paper also looks into optimization and further improvement that can be achieved on existing March test algorithms to increase the fault coverage or to reduce the test complexity.

IEEE Transactions on Computers, 1989

IEEE Transactions on Industrial Electronics, 2000

IEE Proceedings - Computers and Digital Techniques, 2006

The results of 12 well-known and three fault-primitive-based memory test algorithms applied to 0.13 micron technology 512 kB single-port SRAMs are presented. Each test algorithm is used with up to 16 different stress combinations (SCs) (i.e. different address sequences, data backgrounds and voltages) resulting in 122 tests. The results show that SCs influence the fault coverage (FC) of the test algorithms, that the highest FC is obtained at a low voltage level and that the highest detected number of unique faults is obtained at a high voltage level. They also show that the tests with the most promising FC, based on the theory, also tend to have the highest FC in practice. Moreover, the test results show that some algorithms detect faults that cannot be explained with the existing fault models, indicating that the existing fault models still leave much to be explained; for example, no theoretical basis exists to model the stresses and the predicted FC for a given test.

2012

The fast growing of technologies has enabled the Static Random Access Memories (SRAMs) to contain higher density of cell array which make it prone to be affected by defects. This factor contributes to challenges faced in the area of memory testing. Functional test is a standard testing procedure to determine the functionality of the memory by performing a sequence of read write operations to detect faults. March tests are widely used during functional testing due to its higher fault coverage and less time complexity. March tests are developed based on functional fault model (FFM) such as stuck-at faults (SAFs), transition faults (TFs) and coupling faults (CFs). Recent March tests have incorporate a diagnostic capability that enables faults not only to be detected but also distinguished. The diagnosis capability of March tests are verified based on generated fault syndromes dictionary that correspond to the detection of targeted faults during read operations. However, existing March ...

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2002

The authors present test algorithms for go/no-go and diagnostic test of memories, covering neighborhood pattern-sensitive faults (NPSFs). The proposed test algorithms are March based, which have linear time complexity and result in a simple built-in self-test (BIST) implementation. Although conventional March algorithms do not generate all neighborhood patterns to test the NPSFs, they can be modified by using multiple data backgrounds such that all neighborhood patterns can be generated. The proposed multibackground March algorithms have shorter test lengths than previously reported ones, and the diagnostic test algorithm guarantees 100% diagnostic resolution for NPSFs and conventional RAM faults. Based on the proposed algorithms, the authors also present a cost-effective BIST design. The BIST circuit is programmable, and it supports March algorithms, including the proposed multibackground one.

Journal of Electronic Testing, 1996

This paper presents a new methodology for RAM testing based on the PS(n, k) fault model (the k out of n pattern sensitive fault model). According to this model the contents of any memory cell which belongs to an n-bit memory block, or the ability to change the contents, is influenced by the contents of any k-1 cells from this block. The proposed methodology is a transparent BIST technique, which can be efficiently combined with on-line error detection. This approach preserves the initial contents of the memory after the test and provides for a high fault coverage for traditional fault and error models, as well as for pattern sensitive faults. This paper includes the investigation of testing approaches based on transparent pseudoexhaustive testing and its approximations by deterministic and pseudorandom circular tests. The proposed methodology can be used for periodic and manufacturing testing and require lower hardware and time overheads than the standard approaches.

1997

We study the class of "bounded faults" in random-access memories; these are faults that involve a bounded number of cells. This is a very general class of memory faults that includes, for example, the usual stuck-at, coupling, and pattern-sensitive faults, but also many other types of faults. Some bounded faults are known to require deterministic tests of length proportional to n log 2 n, where n is the total number of memory cells. The main result of this paper is that, for any bounded fault satisfying certain very mild conditions, the random test length required for a given level of confidence is always O(n).

Ieee Transactions on Computers, 1990

Abstmct-This paper shows how random testing experiments can be used for fault diagnosis. Starting from a prescribed set of faults, the result of the first experiment allows us 1) to determine a subset of faults which are compatible with this result and 2) to choose the second experiment, and so on.

IEEE Journal of Solid-State Circuits, 1990

Row and column sensitive faults in RAM's are a class of faults in which the contents of a cell become sensitive to the contents of the row and column containing the cell in presence of a fault. In this paper we formally define a fault model to include such faults and present an algorithm to detect faults from this fault model. We then describe two different implementations of the algorithm for a VLSI built-in-self-test (BIST) environment. They are: 1) a random-logic-based design, and 2) a microcode-based design. Finally we identify and list additional properties of the algorithm, such as its capability to detect stuck-at faults, coupling faults, and conventional pattern sensitive faults.