Papers by Ciro Donnarumma
Lecture Notes on Data Engineering and Communications Technologies, 2016
During the last years Field Programmable Gate Arrays and Graphics Processing Units have become in... more During the last years Field Programmable Gate Arrays and Graphics Processing Units have become increasingly important for high-performance computing. In particular, a number of industrial solutions and academic projects are proposing design frameworks based on FPGA-implemented GPU-like compute units. Existing GPU-like core projects provide limited hardware support for shared scratchpad memory and particularly for the problem of bank conflicts, a major source of performance loss with many parallel kernels. In this paper, we present a configurable, GPU-like oriented scratchpad memory with built-in support for bank remapping. The core is fully synthetizable on FPGA with a contained hardware cost. We also validated the presented architecture with a cycle-accurate event-driven emulator written in C++ as well as an RTL simulator tool. Last, we demonstrated the impact of bank remapping and other parameters available with the proposed configurable shared scratchpad memory by evaluating the performance of two real-world parallelized kernels.
2020 IEEE Real-Time Systems Symposium (RTSS)
Almost all functional safety standards that regulate safety-critical domains impose to periodical... more Almost all functional safety standards that regulate safety-critical domains impose to periodically test hardware platforms at run-time. RAM memories are among the fundamental components of computing platforms and are notably subject to faults. Hence, they are also primary components to be tested. Unfortunately, RAM tests are destructive, require to be atomically executed, and are not cheap from a computational perspective. As such, if not properly managed, they can jeopardize the timing performance of a real-time system, especially when running upon a multicore platform. This paper proposes a software architecture to integrate online memory tests on multicore real-time systems. Furthermore, by jointly considering a task model and a safety model based on the EN50129 safety standard, it presents an approach to compute the optimal configuration of memory tests that preserves the system schedulability and guarantees a given tolerable functional failure rate (TFFR). Experimental results show that the proposed approach allows achieving a marginal impact on schedulability while preserving a TFFR that is compatible with the highest safety integrity level specified by the EN50129. Periodic online testing of invariable memories aims at detecting the faults that affect constant data in memory. This is typically done using check-sums or the replication and comparison of the invariable address space. Differently, variable memory tests write a known data pattern in memory, perform some data manipulation, and finally check that the memory content is consistent [5]. This means that these tests overwrite the content of the memory (e.g., data used by a task), which must hence be saved before executing
Reliability and safety are mandatory requirements for safety-critical embedded systems. The desig... more Reliability and safety are mandatory requirements for safety-critical embedded systems. The design of a fault-tolerant system is required in many fields (e.g., railway, automotive, avionics) and redundancy helps in achieving this goal. Redundant systems typically leverage voting techniques applied to the outputs produced by tasks to detect and even tolerate failures. This paper studies the integration of distributed voting protocols in fixed-priority real-time systems from a scheduling perspective. It analyzes two scheduling strategies for implementing voting. One is attractive and friendly for software developers and based on suspending the task execution until the replica provides the data to be voted. The other one is inspired by the Logical Execution Time (LET) paradigm and requires introducing additional tasks in the system to accomplish votingrelated activities. Queuing and delays introduced by inter-replica communication interfaces are also analyzed. Experimental results are ...
EN-50128 Certification-Oriented Design of a Safety-Critical Hard Real-Time Kernel
2019 IEEE International Symposium on Software Reliability Engineering Workshops (ISSREW)
The growing complexity and the need for high safety standards in railways infrastructures are pus... more The growing complexity and the need for high safety standards in railways infrastructures are pushing the infrastructure operators toward the adoption of newer solutions able to exploit modern platforms and state-of-the-art software solutions while guaranteeing safety and timing constraints, and maintaining the compliance with the standards. This paper presents the design guidelines of a novel real-time kernel whose development is based on the Italian use case, highlighting its focus on adherence to the standards.
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Papers by Ciro Donnarumma