Multifunction architectures for RNS processors

IAEME PUBLICATION, 2020

Arithmetic operations like addition and multiplication are the most important part for the computation in signal processing applications. Mathematical operations can be computed with increased speed in Residue Number System (RNS) than the conventional binary number systems because all the operations are done carry free and in parallel in RNS system. These carry free and parallel operations speed up in the RNS based computation. Selection of proper moduli set and their values offer maximum speed and minimum hardware for designing a signal processing system. In Residue Number System many intermediate results are constant and processing time can also be reduced using look-up table. Though there are many limitations in the RNS system, still RNS system can be used to speed up the total execution time of a system in comparison with conventional binary system.

2002

A systematic methodology for designing full-adder-based architectures in Residue Number System for scaling operation and its software tool development, are introduced. Starting from the mathematical description of scaling operation in RNS, we end up with the VHDL description of a full-adder based architecture. The proposed tool was implemented in C++ language and it is available for PC and HP Platforms. The derived architectures are characterized by smaller hardware complexity and higher throughput rates than existing ones.

… , 1998. Proceedings of the 1998 IEEE …, 1998

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IEEJ Transactions on Electronics, Information and Systems, 2005

The multiplier and divider used for specific hardware of public key cryptosystem arithmetic are constructed from many adders and subtractors to improve the accuracy of the key. However, with the increase of accuracy, the propagation delay problem becomes unavoidable. Although some paper have proposed that a divider using redundant binary representation is effective to cope with this problem, no considerations were given to the problems of rounding error and accuracy of the remainder. This paper proposes a method, based on inherent bit sliced architecture, that can cope with these problems and that is expandable to any level of accuracy. It is expected to make it applicable to hardware for public key cryptosystem that can be flexible in coping with the expansion of the key string and the variable length key.

Residue Number System (RNS) allows performing computation more efficiently. Natural parallelism of representation and processing of numbers makes this number system suitable for applying to high performance computing. We address the main features of application of RNS to high-performance parallel computing. We consider and analyze different stages of data processing in RNS. Based on this analysis, we describe the process of decomposition of algorithms using RNS

American Journal of Applied Sciences

Residue Number System (RNS) is an unweighted number system that symbolizes big integers with smaller numbers. It can perform operations in particular addition and multiplication in parallel. Because of this property, RNS is extensively used in communication, Finite Impulse Response (FIR), cryptography and signal processing devices. The transfer of data in digital channels is very important for some critical applications where accuracy is very important. In this study, we proposed a novel algorithm that is premised on the Hamming Distance (HD) and one of the reverse conversion methods, which is, the Chinese Remainder Theorem (CRT) and) as a joint technique for the detection and correction of multiple bit errors in RNS. The proposed algorithm provides a more efficient technique that improves on the hardware size and increases the processing speed with fewer iterations when compared with other stateof-the-art schemes. The work analyses the area and delay of the hardware architecture and compared with other similar schemes. The results indicated the effectiveness of our proposed scheme in terms of the area and delay specifications.

International Journal of Electrical and Computer Engineering (IJECE), 2023

Reversible computing is an emerging technique to achieve ultra-low-power circuits. Reversible arithmetic circuits allow for achieving energy-efficient high-performance computational systems. Residue number systems (RNS) provide parallel and fault-tolerant additions and multiplications without carry propagation between residue digits. The parallelism and fault-tolerance features of RNS can be leveraged to achieve high-performance reversible computing. This paper proposed RNS full reversible circuits, including forward converters, modular adders and multipliers, and reverse converters used for a class of RNS moduli sets with the composite form {2 k , 2 p-1}. Modulo 2 n-1, 2 n , and 2 n +1 adders and multipliers were designed using reversible gates. Besides, reversible forward and reverse converters for the 3-moduli set {2 n-1, 2 n+k , 2 n +1} have been designed. The proposed RNSbased reversible computing approach has been applied for consecutive multiplications with an improvement of above 15% in quantum cost after the twelfth iteration, and above 27% in quantum depth after the ninth iteration. The findings show that the use of the proposed RNS-based reversible computing in convolution results in a significant improvement in quantum depth in comparison to conventional methods based on weighted binary adders and multipliers.

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 2000

The scaled Chinese remainder theorem (CRT) is a very useful tool in residue arithmetic. Its properties can be exploited for the simplification and speeding-up of the conversion process. The main drawback presented by this methodology, when it is used for the output conversion, is the need of long wordlength look-up tables (LUTs) storing the correspondence among the modular numbers and the corresponding scaled terms of the CRT. This fact limits the maximum speed obtainable by this approach. In this brief, a new method for the computation of the scaled terms is presented. It has been implemented by using very small wordlength LUTs and simple arithmetic operators. The only proviso is that the moduli must be odd. The obtained architecture is very fast and due to the local interconnections is suitable for an efficient VLSI implementation.

IEEE Transactions on Circuits and Systems I-regular Papers, 2008

Over the last three decades there has been considerable interest in the implementation of digital computer elements using hardware based on the residue number system, due to the carry free addition and other beneficial characteristics of this system. Scaling operation is one of the essential operations in this number system, and is required for almost every digital signal processing application. Up to now, researchers have suggested costly and low throughput ROM based approaches to address this need. We also address this need by presenting a novel graph-based methodology for designing high throughput and low cost VLSI Residue Number System scaling architectures, based completely on full adders. Our formalized methodology consists of a number of steps, which specify the minimum number of full adders for performing the scaling operation as well as the interconnections among the full adders. We present our formalized methodology together with a running example to aid in comprehension. Negative residue numbers are covered as well, requiring no additional effort. Finally, we have developed a design support tool that can provide structural VHDL descriptions of our residue number system scalers, which can be synthesized in VLSI tools.

2010

As one of the processor's ALU performance issues, the carry propagation during the addition operation limits the speed of arithmetic operation. This work aims to build an Efficient Hardware Design for an Adder based on Residual Numbering System (RNS), with a pre-specified special set of moduli to simplify the implementation for proving the feasibility of its usage. Our design can be divided into three basic components: two conversion modules, and an addition module. The conversion modules here are based on a special set of moduli numbers to simplify the hardware implementation. In this work, we focus on forward conversion (conventional to RNS) leaving reverse converter {RNS to conventional} for future works. Depending on this notion, we implemented each component individually in VHDL and then to assemble these components with each other to build a whole RNS-Adder. Simulation results are very attractive in terms of critical path delay.