Phase-change random access memory: A scalable technology

Advanced Materials, 2014

MRS Proceedings, 2010

By virtue of their unique electronic properties, nanometer-diameter sized single-walled carbon nanotubes represent ideal candidates to function as active parts of nanoelectronic memory storage devices. We show for the first time that GeTe, a phase change material, currently considered to be one of the most promising materials for data-storage applications, can efficiently be encapsulated within single-walled carbon nanontubes of 1.4 nm diameter. Structural investigations on the encapsulated GeTe nanowires have been carried out by high resolution transmission electron microscopy. The electronic interactions between the filling material and the host nanotube have been examined using ultraviolet photoelectron spectroscopy experiments and show that the electronic structure of the encapsulating nanotube and that of the encased filling are not perturbed by the presence of each of the other component.The newly formed hybrids offer potential to operate as active elements in non-volatile ele...

New Journal of Physics, 2014

Phase-change memory technology has become more mature in recent years. But some fundamental problems linked to the electrical transport properties in the amorphous phase of phase-change materials still need to be solved. The increase of resistance over time, called resistance drift, for example, poses a major challenge for the implementation of multilevel storage, which will eventually be necessary to remain competitive in terms of high storage densities. To link structural properties with electrical transport, a broader knowledge of (i) changes in the density of states (DoS) upon structural relaxation and (ii) the influence of defects on electrical transport is required. In this paper, we present temperaturedependent conductivity and photo-conductivity measurements on the archetype phase change material GeTe. It is shown that trap-limited band transport at high temperatures (above 165 K) and variable range hopping at low temperatures are the predominating transport mechanism. Based on measurements of the temperature dependence of the optical band gap, modulated photo-conductivity and photo-thermal deflection spectroscopy, a DoS model for GeTe was proposed. Using this DoS, the temperature dependence of conductivity and photo-conductivity has been simulated. Our work shows how changes in the DoS (band gap and defect distributions) will affect the electrical transport before and after

Review of Scientific Instruments, 2009

Encapsulated conducting probes that can sustain high currents are used to study the nanoscale properties of thin-film stacks comprising of a phase-change chalcogenide, Ge 2 Sb 2 Te 5. Scaling studies on this promising candidate for random-access memory devices had thus far required extensive lithography and nanoscale growth. This seriously hampers rapid materials characterization. This article describes the use of two key techniques, an encapsulated conductive probe and its use in retraction mode, whereby the attractive force between tip and sample is used to maintain electrical contact. The effective transformation of nanoscale dots of amorphous Ge 2 Sb 2 Te 5 into the crystalline state is achieved and the electrical conductivity of the transformed structures is probed. The use of retraction force microscopy in a robust manner is demonstrated by reading the conductivity of the crystalline dots. Both these techniques could enable rapid electrical characterization of nanoscale materials, without extensive nanopatterning, thus reducing material development cycles.

Proceedings of the International Symposium on Memory Systems - MEMSYS '19, 2019

The demand on memory capacity from applications has always challenged the available technologies. It is therefore important to understand that this demand and the consequential limitations in various aspects led to the appearance of new memory technologies and system designs. Fundamentally, not a single solution has managed to fully solve this memory capacity challenge. As argued in this survey paper, limitations by physical laws make the effort of expanding local off-chip memory impossible without adopting new approaches. The concept of Non Unified Memory Access (NUMA) architecture provides more system memory by using pools of processors, each with their own memories, to workaround the physical constraints on a single processor, but the additional system complexities and costs led to various scalability issues that deter any further system expansion using this method. Computer clusters were the first configurations to eventually provide a Distributed Shared Memory (DSM) system at a linear cost while also being more scalable than the traditional cache coherent NUMA systems, however this was achieved by using additional software mechanisms that introduce significant latency when accessing the increased memory capacity. As we describe, since the initial software DSM systems, a lot of effort has been invested to create simpler and higher performance solutions including: software libraries, language extensions, high performance interconnects and abstractions via system hypervisors, where each approach allows a more efficient way of memory resource allocation and usage between different nodes in a machine cluster. Despite such efforts, the fundamental problems of maintaining cache coherence across a scaled system with thousands of nodes is not something that any of the current approaches are capable of efficiently providing, and therefore the requirement of delivering a scalable memory capacity still poses a real challenge for system architects. New design concepts and technologies, such as 3D stacked

Advanced Materials

Reconfigurability of photonic integrated circuits (PICs) has become increasingly important due to the growing demands for electronic-photonic systems on a chip driven by emerging applications, including neuromorphic computing, quantum information, and microwave photonics. Success in these fields usually requires highly scalable photonic switching units as essential building blocks. Current photonic switches, however, mainly rely on materials with weak, volatile thermo-optic or electro-optic modulation effects, resulting in large footprints and high energy consumption. As a promising alternative, chalcogenide phase-change This article is protected by copyright. All rights reserved. 2 materials (PCMs) exhibit strong optical modulation in a static, self-holding fashion, but the scalability of present PCM-integrated photonic applications is still limited by the poor optical or electrical actuation approaches. Here, with phase transitions actuated by in-situ silicon PIN heaters, scalable nonvolatile electrically reconfigurable photonic switches using PCM-clad silicon waveguides and microring resonators are demonstrated. As a result, intrinsically compact and energy-efficient switching units operated with low driving voltages, near-zero additional loss, and reversible switching with high endurance are obtained in a complementary metal-oxide-semiconductor (CMOS)-compatible process. This work can potentially enable very large-scale CMOS-integrated programmable electronic-photonic systems such as optical neural networks and general-purpose integrated photonic processors. Advances in PICs, in particular, silicon photonics, have enabled chip-scale integration of photonic systems with electronic circuits. [1] As Moore's Law slows down and the electronic von Neumann bottleneck (i.e. the information traffic jam between the memory and processor) gets worse, these photonic systems are becoming more and more attractive by offering broad bandwidth with energy-efficient information transport, processing, and storage. [2] They are especially desirable when it comes to emerging applications such as neuromorphic computing, [3] quantum information, [4,5] and microwave photonics, [6,7] most of which require general-purpose programmable PICs. [8-10] Inspired by the field-programmable gate arrays (FPGAs) in electronics, such generic PICs or optical FPGAs usually consist of a mesh of photonic switches that can be reconfigured on demand to the bar, cross, or coupler states [8-10] to provide different functionalities, including universal linear transformation. [9,10] Current switches in these photonic systems, however, primarily rely on thermo-optic [11] or electrooptic [12,13] modulation effects that are weak and volatile. The resulting large footprint and constant high energy consumption thus restrict the scalability of such optical FPGAs.

Proceedings of the 17th International Workshop on Data Management on New Hardware (DaMoN 2021), 2021

Storage devices have evolved to offer increasingly faster read/write access, through flash-based and other solid-state storage technologies. When compared to classical rotating hard disk drives (HDDs), modern solid-state drives (SSDs) have two key differences: (i) the absence of mechanical parts, and (ii) an inherent difference between the process of reading and writing. The former removes a key performance bottleneck, enabling internal device parallelism, whereas the latter manifests as a read/write performance asymmetry. In other words, SSDs can serve multiple concurrent I/Os, and their writes are generally slower than reads; none of which is true for HDDs. Yet, the performance of storage-resident applications is typically modeled by the number of disk accesses performed, inherently assuming symmetric read and write performance and the ability to perform only one I/O at a time, failing to accurately capture the performance of modern storage devices. To address this mismatch, we pr...

Proceedings of the 17th International Workshop on Data Management on New Hardware (DaMoN 2021), 2021

Bloom filters (BFs) accelerate point lookups in Log-Structured Merge (LSM) trees by reducing unnecessary storage accesses to levels that do not contain the desired key. BFs are particularly beneficial when there is a significant performance difference between querying a BF (hashing and accessing memory) and accessing data (on secondary storage). This gap, however, is decreasing as modern storage devices (SSDs and NVMs) have increasingly lower latency, to the point that the cost of accessing data can be comparable to that of filter probing and hashing, especially for large key sizes that exhibit high hashing cost. In an LSM-tree, BFs are employed when querying each level of the tree, thus, exacerbating the CPU cost as the data size - and thus, the tree height - grows. To address the increasing CPU cost of BFs in LSM-trees, we propose to re-use hash calculations aggressively within and across BFs, as well as between different levels, and we show both analytically and experimentally th...

ACM Journal on Emerging Technologies in Computing Systems

Currently, data-intensive applications are gaining popularity. Together with this trend, processing-in-memory (PIM)–based systems are being given more attention and have become more relevant. This article describes an analytical modeling tool called Bitlet that can be used in a parameterized fashion to estimate the performance and power/energy of a PIM-based system and, thereby, assess the affinity of workloads for PIM as opposed to traditional computing. The tool uncovers interesting trade-offs between, mainly, the PIM computation complexity (cycles required to perform a computation through PIM), the amount of memory used for PIM, the system memory bandwidth, and the data transfer size. Despite its simplicity, the model reveals new insights when applied to real-life examples. The model is demonstrated for several synthetic examples and then applied to explore the influence of different parameters on two systems — IMAGING and FloatPIM. Based on the demonstrations, insights about PIM...

Journal of Electronic Packaging, 2020

This review introduces relevant nanoscale thermal transport processes that impact thermal abatement in power electronics applications. Specifically, we highlight the importance of nanoscale thermal transport mechanisms at each layer in material hierarchies that make up modern electronic devices. This includes those mechanisms that impact thermal transport through: (1) substrates, (2) interfaces and two-dimensional materials, and (3) heat spreading materials. For each material layer, we provide examples of recent works that (1) demonstrate improvements in thermal performance and/or (2) improve our understanding of the relevance of nanoscale thermal transport across material junctions. We end our discussion by highlighting several additional applications that have benefited from a consideration of nanoscale thermal transport phenomena, including radio frequency (RF) electronics and neuromorphic computing. [DOI: 10.1115/1.4049293]

Wireless Personal Communications, 2018

Persistent memory has the potential to become universal storage for memory and storage uses. Unfortunately, our system architecture is good fit for two-level storage model with DRAM and storage. It incurs two of important performance overheads. First is higher latency and degrading concurrent performance due to the requirements of persistence and consistency of persistent memory. Another is to abstract in-memory objects into file although these in-memory objects are already persistent, or to load data objects from files even they are in memory. We propose a hybrid storage model with a persistent objects management system to manage in-persistent memory data sets. Persistent memory plays dual roles of memory and storage, CPU directly access in-persistent memory data sets, and these data sets are not required serializing or de-serializing into files, managed by persistent object management system. To lower overheads introduced by high latency and consistence of persistent memory, DRAM is used as buffer, shifting persistency and consistence from each application to our management process, named persistent memory server engine. The experiment results show that our prototype can benefit file-intensive, data-intensive applications and relational databases, providing 15-63% better performance than persistent heap and persistent memory file systems using direct access method.

Journal of Computer Science and Technology, 2019

New non-volatile memory (NVM) technologies are expected to replace main memory DRAM (dynamic random access memory) in the near future. NAND flash technological breakthroughs have enabled wide adoption of solid state drives (SSDs) in storage systems. However, flash-based SSDs, by nature, cannot avoid low endurance problems because each cell only allows a limited number of erasures. This can give rise to critical SSD reliability issues. Since many SSD write operations eventually cause many SSD erase operations, reducing SSD write traffic plays a crucial role in SSD reliability. This paper proposes two NVM-based buffer cache policies which can work together in different layers to maximally reduce SSD write traffic: a main memory buffer cache design named Hierarchical Adaptive Replacement Cache (H-ARC) and an internal SSD write buffer design named Write Traffic Reduction Buffer (WRB). H-ARC considers four factors (dirty, clean, recency, and frequency) to reduce write traffic and improve cache hit ratios in the host. WRB reduces block erasures and write traffic further inside an SSD by effectively exploiting temporal and spatial localities. These two comprehensive schemes significantly reduce total SSD write traffic at each different layer (i.e., host and SSD) by up to 3x. Consequently, they help extend SSD lifespan without system performance degradation.

MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Resistive memories (ReRAM) organized in the form of crossbars are promising for main memory integration. While offering high cell density, crossbar-based ReRAMs suffer from variable write latency requirement for RESET operations due to the varying impact of IR drop, which jointly depends on the data pattern of the crossbar and the location of target cells being RESET. The exacerbated worst-case RESET latencies can significantly limit system performance. In this paper, we propose LADDER, an effective and low-cost processor-side framework that performs writes with variable latency by exploiting both content and location dependencies. To enable content awareness, LADDER incorporates a novel scheme that maintains metadata for per-row data pattern (i.e., number of 1's) in memory, and performs efficient metadata management and caching through the memory controller. LADDER does not require hardware changes to the ReRAM chip. We design several optimizations that further boost the performance of LADDER, including LRS-metadata estimation that eliminates stale memory block reads, intra-line bit-level shifting that reduces the worst-case LRS-counter values and multi-granularity LRS-metadata design that optimizes the number of counters to maintain. We evaluate the efficacy of LADDER using 16 single-and multi-programmed workloads. Our results show that LADDER exhibits on average 46% performance improvement as compared to a baseline scheme and up to 33% over state-of-the-art designs. Furthermore, LADDER achieves 28.8% average dynamic memory energy saving compared to the existing architecture schemes and has less than 3% impact on device lifetime. CCS CONCEPTS • Hardware → Non-volatile memory; Emerging architectures; • Computer systems organization → Processors and memory architectures.

Proceedings of the 26th Symposium on Operating Systems Principles, 2017

Emerging fast, persistent memories will enable systems that combine conventional DRAM with large amounts of nonvolatile main memory (NVMM) and provide huge increases in storage performance. Fully realizing this potential requires fundamental changes in how system software manages, protects, and provides access to data that resides in NVMM. We address these needs by describing an NVMM-optimized file system called NOVA-Fortis that is both fast and resilient in the face of corruption due to media errors and software bugs. We identify and propose solutions for the unique challenges in adding fault tolerance to an NVMM file system, adapt state-of-the-art reliability techniques to an NVMM file system, and quantify the performance and storage overheads of these techniques. We find that NOVA-Fortis' reliability features consume 14.8% of the storage for redundancy and reduce application-level performance by between 2% and 38% compared to the same file system with the features removed. NOVA-Fortis outperforms DAX-aware file systems without reliability features by 1.5× on average. It outperforms reliable, block-based file systems running on NVMM by 3× on average.

Materials

In this paper, a thorough characterization of phase-change memory (PCM) cells was carried out, aimed at evaluating and optimizing their performance as enabling devices for analog in-memory computing (AIMC) applications. Exploiting the features of programming pulses, we discuss strategies to reduce undesired phenomena that afflict PCM cells and are particularly harmful in analog computations, such as low-frequency noise, time drift, and cell-to-cell variability of the conductance. The test vehicle is an embedded PCM (ePCM) provided by STMicroelectronics and designed in 90-nm smart power BCD technology with a Ge-rich Ge-Sb-Te (GST) alloy for automotive applications. On the basis of the results of the characterization of a large number of cells, we propose an iterative algorithm to allow multi-level cell conductance programming, and its performances for AIMC applications are discussed. Results for a group of 512 cells programmed with four different conductance levels are presented, sho...

ACM Transactions on Embedded Computing Systems, 2016

In this article, we study the indexing problem of using PCM as the storage medium for embedded multiversion databases in cyber-physical systems (CPSs) . Although the multiversion B + -tree (MVBT) index has been shown to be efficient in managing multiple versions of data items in a database, MVBT is designed for databases residing in traditional block-oriented storage devices. It can have serious performance problems when the databases are on phase-change memory (PCM) . Since the embedded multiversion database in CPSs may have limited storage space and are update intensive, to resolve the problems of MVBT of lack of space efficiency and heavy update cost, we propose a new index scheme, called space-efficient multiversion index (SEMI) , to enhance the space utilization and access performance in serving various types of queries. In SEMI, since the number of keys in the database may be small, instead of using a B -tree index, we propose to use a binary-search tree to organize the index ...

Applied Physics Letters, 2020

This work elucidates the role of interface states of a metal-oxide-silicon device, the basic structure of CMOS integrated resistive random access memory (ReRAM) devices. By fabricating Au/Al 2 O 3 /Si ReRAM devices on silicon substrates oriented along h100i and h111i directions and employing the frequency dependence of capacitance and parallel conductance, we explore the role of interface trap densities (D it) in the breakdown mechanism of ReRAM devices. In order to quantify the interface states, we measured the parallel conductance of the ReRAM devices as a function of frequency, which gives an accurate picture of the spread of D it along the bandgap of silicon. Analysis of interface state density before and after the breakdown process reveals that the Si h111i surface is more prone to generate defects than Si h100i surfaces, and its elucidation is done by analyzing the pre-breakdown current behavior of the devices. Finally, the influence of the interface states on the thickness scaling is shown, where the thinner devices are inclined to have an earlier breakdown (Set voltage) due to the strong coupling with interface states.

ACM Transactions on Architecture and Code Optimization, 2019

Superpages have long been used to mitigate address translation overhead in large-memory systems. However, superpages often preclude lightweight page migration, which is crucial for performance and energy efficiency in hybrid memory systems composed of DRAM and non-volatile memory (NVM). In this article, we propose a novel memory management mechanism called Rainbow to bridge this fundamental conflict between superpages and lightweight page migration. Rainbow manages NVM at the superpage granularity, and uses DRAM to cache frequently accessed (hot) small pages within each superpage. Correspondingly, Rainbow utilizes split TLBs to support different page sizes. By introducing an efficient hot page identification mechanism and a novel NVM-to-DRAM address remapping mechanism, Rainbow supports lightweight page migration without splintering superpages. Experiment results show that Rainbow can significantly reduce applications’ TLB misses by 99.9%, and improve application performance (in ter...

Communications in Computer and Information Science, 2020

Page migration has long been adopted in hybrid memory systems comprising dynamic random access memory (DRAM) and non-volatile memories (NVMs), to improve the system performance and energy efficiency. However, page migration introduces some side effects, such as more translation lookaside buffer (TLB) misses, breaking memory contiguity, and extra memory accesses due to page table updating. In this paper, we propose superpagefriendly page table called SuperPT to reduce the performance overhead of serving TLB misses. By leveraging a virtual hashed page table and a hybrid DRAM allocator, SuperPT performs address translations in a flexible and efficient way while still remaining the contiguity within the migrated pages.

Journal of Applied Physics

This article presents three photothermal methods dedicated to the measurement of the thermal properties of chalcogenide alloys, used as a central element in the new generations of non-volatile memory. These materials have two phases, amorphous and crystalline, possessing a sharp contrast in their electrical and thermal properties. In the crystalline phase, the properties also change very significantly with temperature. The control of the temperature of the samples, the choice of transducers, and the time or frequency characteristic values of the photothermal excitation are thoroughly discussed. Each photothermal technique is described from the experimental point of view as well as from the inverse method, performed to identify the parameters of interest. The identified thermal properties mainly concern the thermal conductivity and the thermal resistance at the interfaces between the phase-change materials and the materials in contact as encountered in the production of the microelectronic memory device. Assessing various photothermal techniques, the study suggests that pulsed photothermal radiometry is the most effective method for sensitive high-temperature measurements of thermal properties of the phase-change materials.

Nanomaterials, 2020

We experimentally investigated the effect of post-growth annealing on the morphological, structural, and electrophysical parameters of nanocrystalline ZnO films fabricated by pulsed laser deposition. The influence of post-growth annealing modes on the electroforming voltage and the resistive switching effect in ZnO nanocrystalline films is investigated. We demonstrated that nanocrystalline zinc oxide films, fabricated at certain regimes, show the electroforming-free resistive switching. It was shown, that the forming-free nanocrystalline ZnO film demonstrated a resistive switching effect and switched at a voltage 1.9 ± 0.2 V from 62.42 ± 6.47 (RHRS) to 0.83 ± 0.06 kΩ (RLRS). The influence of ZnO surface morphology on the resistive switching effect is experimentally investigated. It was shown, that the ZnO nanocrystalline film exhibits a stable resistive switching effect, which is weakly dependent on its nanoscale structure. The influence of technological parameters on the resistive ...

Journal of Alloys and Compounds

The compound GeTe, despite its simple stoichiometry, is rather unconventional and has been investigated both from a fundamental and technological perspective: it is of high interest for several technologies such as data-storage (phase change memories) and thermoelectricity. The understanding of GeTe growth is thus a key issue for technological applications and fundamental understanding. In this work, GeTe crystallization kinetics is compared to Ge/Te reactive diffusion kinetics using in situ X-ray diffraction measurements, as well as in situ transmission electron microscopy. GeTe crystallization from an amorphous solid solution exhibiting the stoichiometry of the compound GeTe is found to occur at the same temperature as for the reactive diffusion of an amorphous Ge layer on top of a polycrystalline Te layer. Furthermore, GeTe growth is of tridimensional type in the two cases, and can be modeled by the Johnson-Mehl-Avrami-Kolmogorov model. Using this model, the activation energies of nucleation and growth were determined for both crystallization and reactive diffusion. The results suggest that GeTe exhibits nucleation/reaction kinetics unusually low compared to atomic transport kinetics, contrasting with other germanides.

Proceedings of the International Symposium on Memory Systems

Mobile devices run on small batteries with limited capacities. Hence, energy consumption is an important factor that determines the duration of a mobile device's usage. Main memory consumes a significant portion of the total system energy especially when the mobile device is idle, which is the case most of the times. Moreover, in current and future systems, it is very likely that users tend to run various mobile applications simultaneously, which further increases the aggregate memory demands of mobile devices. Therefore, optimizations on memory energy consumption have become even more critical in those devices. In this paper, we propose a novel scheme called NEMO to improve the energy efficiency of mobile devices with a hybrid DRAM/PCM main memory. Our scheme powers off as many power-hungry DRAM components as possible, as long as it does not impact the performance. Specifically, when the mobile device is in idle state, only a selective set of data that is critical to performance is kept in a single DRAM rank, while the rest of data is stored in PCM, so that the remaining DRAM ranks can be powered off. To do so, NEMO classifies memory pages based on their usage frequency and recency into hot and cold. Then, it places the hot pages that are more likely to be reused in future in the DRAM, which has lower access latency compared to PCM, and stores cold memory pages in PCM, which has near-zero idle power. In addition, NEMO predicts the number of DRAM ranks that need to be powered on when the mobile device becomes active for further energy saving. Our simulation results reveal that NEMO achieves on average, 10.2% reduction in memory power consumption and 1.7% performance improvement on a system running various combinations of Moby benchmark applications with 128MB DRAM and 1GB PCM, compared with the approach that simply puts DRAM into self-refresh low-power mode during idle state.

physica status solidi (b), 2017

The thermal stress effect on the structure of phase change memory materials, namely single films and double stacked films of GeTe and SnSe, is evaluated. The crystallization temperatures of GeTe and SnSe single films are 138 °C and 292 °C, respectively. The films are amorphous before annealing and crystallize in rhombohedral and orthorhombic structures afterwards. Ge is tetrahedrally bonded and Se is bivalent after deposition. Both Ge and Se have an octahedral configuration after annealing. The double stacked structure is studied in the as‐deposited state and after annealing at temperatures of 100, 210, and 350 °C. Pulsed laser deposition produces the crystallization of both as‐deposited layers when stacked, mostly of SnSe, but also some crystalline GeTe is present. GeTe fully crystallizes after annealing at 210 °C, in the face‐centred cubic structure. Annealing at 350 °C leads to the evaporation of a significant quantity of Se and to the formation of a cubic Ge0.75Sn0.25Te solid so...

Philosophical Magazine, 2018

We have investigated the effect of thermal annealing on the structure of single and stacked phase change memory films based on SnSe and GaSb. Samples were prepared by pulsed laser deposition and investigated by X-ray absorption spectroscopy (XAS) and X-ray diffraction (XRD) methods. Electrical resistance versus temperature investigations showed crystallisation temperatures of 292°C and 198°C for SnSe and GaSb single films, respectively. Above the transition temperature, GaSb crystallises into a facecentered cubic structure, whereas SnSe has an orthorhombic arrangement. Annealing at three temperatures (160°C, 250°C and 350°C) of the SnSe\GaSb stacked films promotes bond breaking, atom diffusion between the two layers and formation of new phases. At 160°C, GaSb films crystallise partially and no effect is observed on the crystallinity of SnSe films. After 250°C, rhombohedral SnSb emerges in addition to GaSb complete crystallisation. A major, completely new, body-centered orthorhombic unindexed quaternary Ga-Sn-Sb-Se phase formation was observed in the samples annealed at 350°C. The GaSb crystallites are fully dissolved and we have observed the formation of a minor hexagonal SnSe 2 phase. The analysis of EXAFS data, measured at Se and Ga K-edges, revealed changes in the local atomic environment as a function of the annealing temperature. A tetrahedral configuration is obtained for the Ga atoms in both asdeposited and annealed samples, whereas Se is mostly bivalent in the amorphous samples and has an octahedral arrangement in crystalline SnSe. Our results show that interlayer diffusion should always be considered and evaluated when designing memory cells composed of stacked phase change chalcogenide films.

Proceedings of the International Symposium on Memory Systems, 2017

The quest for greater performance and efficiency has driven modern cloud applications towards "in-memory" implementations, such as memcached and Apache Spark. Looking forward, however, the costs of DRAM, due to its low area density and high energy consumption, may make this trend unsustainable. Traditionally, OS paging system mechanisms were intended to bridge the gap between expensive, under-provisioned DRAM and inexpensive, dense storage, however, in the past twenty years the latency of storage, relative to DRAM became too great to overcome without significant performance impact. Recent NVM storage devices, such as Intel Optane drives and aggressive, 3D flash SSDs, may dramatically change the picture for OS paging. These new drives are expected to provide much lower latency compared to the existing flash-based SSDs or traditional HDDs. Unfortunately, even these future NVM drives are still much too slow to replace DRAM, since the access latency of fast NVM storage is expected on the order of tens of microseconds, and they often require block-level access. Unlike traditional HDDs, for which the baseline OS paging policies are designed, these new SSDs place no penalty for "random" access and their access latency promises to be significantly less than traditional SSDs, thus arguing for a rearchitecting of the OS paging system. In this paper, we propose SPAN (Speculative PAging for future NVM storage), a software-only, OS swap-based, page management and prefetching scheme designed for emerging NVM storage. Unlike the baseline OS swapping mechanism, which is highly optimized for traditional spinning disks, SPAN leverages the inherent parallelism of NVM devices to proactivley fetch a set of pages from NVM storage to the small and fast main DRAM. In doing so, SPAN yields a speedup of ∼18% versus swapping into the NVM with the baseline OS (∼50% of the performance lost by the baseline OS versus placing the entire working set in DRAM memory). The proposed technique thus enables the utilization of such hybrid systems for memory-hungry applications, lowering the memory cost while keeping the performance comparable to the DRAM-only system.

ACM Transactions on Embedded Computing Systems

Hybrid memory systems, comprised of emerging non-volatile memory (NVM) and DRAM, have been proposed to address the growing memory demand of current mobile applications. Recently emerging NVM technologies, such as phase-change memories (PCM), memristor, and 3D XPoint, have higher capacity density, minimal static power consumption and lower cost per GB. However, NVM has longer access latency and limited write endurance as opposed to DRAM. The different characteristics of distinct memory classes render a new challenge for memory system design. Ideally, pages should be placed or migrated between the two types of memories according to the data objects’ access properties. Prior system software approaches exploit the program information from OS but at the cost of high software latency incurred by related kernel processes. Hardware approaches can avoid these latencies, however, hardware’s vision is constrained to a short time window of recent memory requests, due to the limited on-chip reso...