Quantum Cost Optimization for Reversible Carry Skip BCD Adder

International Journal of Computer Applications, 2017

In today's world , power dissipation is one of the major concern as the complexity of the chip is increasing and more devices are being integrated on a single chip. Thus this high density of chip and increased power dissipation demands for better power optimization methods. Reversible logic is one of the method to reduce power dissipation. Reversible computing has a wide number of applications in areas of advance computing such as low power CMOS VLSI design, nanotechnology, cryptography, optical computing, DNA computing and quantum computing. This paper presents improved and logic efficient reversible four bit carry skip adder block. The performance of the proposed architecture is better in terms of number of transistors, garbage outputs, constant inputs and gate count when compared with existing works. Also the design forms the basis for different quantum ALU and reversible processors.

Over the last few decades, research in reversible logic has increasingly become very popular and it is gaining greater momentum in the present word. Reversible logic has started finding concert applications in quantum computing, optical computing, nano-technology based system, low-power CMOS design, VLSI design. The principal objective of this work is to argue for quantum implementation of various reversible logic gates by using C-NOT, Controlled-V and Controlled-V + gates. The present work presents Binary coded decimal adder (BCD) in terms of number of gates, garbage outputs, quantum cost, delay and hardware complexity compared to existing design.

2008

Abstract: Reversible logic circuits have found emerging attention in nanotechnology, quantum computing and low power CMOS designs. In this paper we present a modular synthesis method to realize a reversible Binary Coded Decimal (BCD) adder/subtractor circuit. We use genetic algorithms and don't care concept to design and optimize all parts of a BCD adder circuit in terms of number of garbage inputs/outputs and the quantum cost.

IJRET, 2012

Reversible logic has emerged as one of the most important approaches for the power optimization with its application in low power VLSI design. They are also the fundamental requirement for the emerging field of the Quantum computing having with applications in the domains like Nano-technology, Digital signal processing, Cryptography, Communications. Implementing the reversible logic has the advantages of reducing gate counts, garbage outputs as well as constant inputs. In contrast to conventional gates, reversible logic gates have the same number of inputs and outputs, each of their output function is equal to 1 for exactly half its input assignments and their fan-out is always equal to 1. It is interesting to compare both reversible and conventional gates. In this paper addition, subtraction, operations are realized using reversible logic gates like DKG and TSG gate and compared with conventional gates

TJPRC, 2013

Filters are widely used in the world of communication and computation. To design a finite impulse response (FIR) filter that satisfies all the required conditions is a challenge. Power consumption by the multiplier and adder blocks in the architecture is the prime cause for concern in FIR design. In this paper, design of an FIR filter entirely using Reversible logic is presented. Reversible logic is emerging as a promising computing paradigm having widespread areas of application. It is based on the fundamental that zero energy dissipation would be achieved if the design is made of reversible gates. Furthermore, majority of the design is made of Peres gate which has the least quantum cost of all the existing reversible gates. Thus, this paper presents the first and novel approach in realizing an FIR filter that can overcome the problem of power dissipation. The first and foremost approach in designing a low pass FIR filter entirely using reversible logic is presented in this paper. The design is the most novel for it, dominantly makes use of a Peres Gate (quantum cost = 4) in the realization of the multiplier and adder blocks which form major components of the FIR filter block. Power dissipation, the most vital issue in the design of a circuit, can be resolved to the maximum extent by following the proposed implementation.

Proceedings of the Conference on Advances in Communication and Control Systems-2013, 2013

Reversible logic has received great attention in the recent years due to their ability to reduce the power dissipation which is the main requirement in low power digital design. It has wide applications advanced computing, low power CMOS design, Optical information processing, DNA computing, bio information, quantum computation and nanotechnology. This paper presents an optimized reversible BCD adder using a new reversible gate. A comparative result is presented which shows that the proposed design is more optimized in terms of number of gates, number of garbage outputs and quantum cost than the existing designs.

The addition of two binary numbers is the important and most frequently used arithmetic process on microprocessors, digital signal processors (DSP), and data-processing application-specific integrated circuits (ASIC). Therefore, binary adders are critical structure blocks in very large-scale integrated (VLSI) circuits. Their effective application is not trivial because a costly carry spread operation involving all operand bits has to be achieved. Many different circuit constructions for binary addition have been planned over the last decades, covering a wide range of presentation characteristics. In today era, reversibility has become essential part of digital world to make digital circuits more efficient. In this paper, we have proposed a new method to reduce quantum cost for ripple carry adder and carry skip adder. The results are simulated in Xilinx by using VHDL language.

This paper proposes the design of 4-bit adder and implementation of adder Reversible logic gate to improve the design in terms of garbage outputs and delay. In the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology and optical computing because of it’s zero power dissipation under ideal conditions. Thus, the project will provide the reversible logic implementation of the conventional 4-bit adder using Toffoli gate, Peres gate and using both Peres gate and Fredkin gate. The proposed reversible logic implementation of the 4- bit adder is optimized to obtain minimum number of logic gates and garbage outputs. This project work on the reversible 4-bit adder circuits designed and proposed here form the basis of the decimal ALU of a primitive quantum CPU. The designed and optimized 4-bit reversible adder is implemented in VHDL Using Xilinx ISE 12.1 tool.

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002, 2002

Conservative and reversible logic gates are widely known to be compatible with revolutionary computing paradigms such as optical and quantum computing. A fundamental conservative reversible logic gate is the Fredkin gate. This paper presents efficient adder circuits based on the Fredkin gate. Novel full adder circuits using Fredkin gates are proposed which have lower hardware complexity than the current state-of-the-art, while generating the additional signals required for carry skip adder architectures. The traditional ripple carry adder and several carry skip adder topologies are compared. Theoretical performance of each adder is determined and compared. Although the variable sized block carry skip adder is determined to have shorter delay than the fixed block size carry skip adder, the performance gains are not sufficient to warrant the required additional hardware complexity.

2015

— At the present time reversible logic is one of the most significant topic and it has different areas for its application. It is very essential to construct low power, low loss computational structures which are very essential for the construction of arithmetic circuits used in nanotechnology, quantum computation and many other low power circuits. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. This paper represents an another way for designing of 4-bit carry skip BCD adder using DKFG reversible logic gates. The proposed circuit has a lower quantum cost compared to the other existing circuits.