Flexible use of IP gores on dynamically reconfigurable systems

Journal of Systems Architecture, 2006

Run-time partial reconfiguration of programmable hardware devices can be applied to enhance many applications in high-end embedded systems, particularly those that employ recent platform FPGAs. The effective use of this approach is often hampered by the complexity added to the system development process and by limited tool support.

Signal Processing-image Communication, 2010

This paper describes a dynamic partial reconfiguration (DPR) design flow and environment for image and signal processing algorithms used in adaptive applications. Based on the evaluation of the existing DPR design flow, important features such as overall flexibility, application and standardised interfaces, host applications and DPR area/size placement have been taken into consideration in the proposed design flow and environment. Three intellectual property (IP) cores used in pre-processing and transform blocks of compression systems including colour space conversion (CSC), two-dimensional biorthogonal discrete wavelet transform (2-D DBWT) and three-dimensional Haar wavelet transform (3-D HWT) have been selected to validate the proposed DPR design flow and environment. Results obtained reveal that the proposed environment has a better solution providing: a scriptable program to establish the communication between the field programmable gate array (FPGA) with IP cores and their host application, power consumption estimation for partial reconfiguration area and automatic generation of the partial and initial bitstreams. The design exploration offered by the proposed DPR environment allows the generation of efficient IP cores with optimised area/speed ratios. Analysis of the bitstream size and dynamic power consumption for both static and reconfigurable areas is also presented in this paper.

International Parallel and Distributed Processing Symposium/International Parallel Processing Symposium, 2006

The effective use of dynamic reconfiguration requires the designer to address many implementation issues. The market introduction of feature-full platform FPGAs equipped with embedded CPU blocks expands the number of situations where dynamic reconfiguration may be applied to improve overall performance and logic utilization. The paper compares the design of two similar systems supporting dynamic reconfiguration and the issues that were addressed in their implementation. The first system supports 32-bit data transfers between CPU and the dynamically reconfigurable circuits. The other implementation supports 64-bit transfers, but its effective use is more complicated and several restrictions must be taken into account. The work includes a performance comparison of the two designs on several simple tasks, including pattern matching, image processing and hashing

2016

During recent years much research focused on making Partial Reconfiguration (PR) more widespread. The FASTER project aimed at realizing an integrated toolchain that assists the designer in the steps of the design flow that are necessary to port a given application onto an FPGA device. The novelty of the framework lies in the use of partial dynamic reconfiguration seen as a first class citizen throughout the entire design flow in order to exploit FPGA device potential. The STMicroelectronics SPEAr development platform combines an ARM pro-cessor alongside with a Virtex-5 FPGA daughter-board. While partial reconfigura-tion in the attached board was considered as feasible from the beginning, there was no full implementation of a hardware architecture using PR. This work describes our efforts to exploit PR on the SPEAr prototyping embedded platform. The pa-per discusses the implemented architecture, as well as the integration of Run-Time System Manager for scheduling (run-time reconfiogu...

Iet Computers and Digital Techniques, 2007

This paper describes a tool that creates partiallyreconfigurable modules from the bitstreams of individual component modules. The resulting modules are intended for use in applications that exploit partial dynamic reconfiguration. The tool is integrated in a design flow particularly aimed at dynamically-reconfigurable platform FPGAs. The corresponding design flow is described together with a basic run-time support system.

Journal of Signal Processing Systems, 2012

Day after day, embedded systems add more compute-intensive applications inside their end products: cryptography or image and video processing are some examples found in leading markets like consumer electronics and automotive. To face up these ever-increasing computational demands, the use of hardware accelerators synthesized in field-programmable gate arrays (FPGA) lets achieve processing speedups of orders of magnitude versus their counterpart CPU-based software approaches. However, the inherent increment in physical resources penalizes in cost. To address this issue, dynamically reconfigurable hardware technology definitively reached its maturity. SRAM-based reconfigurable logic goes beyond the classical conception of static hardware resources distributed in space and held invariant for the entire application life cycle; it provides a new design abstraction featured by the temporal partitioning of such resources to promote their continuous reuse, reconfiguring them on the fly to play a different role in each instant. This new computing paradigm lets balance the design of embedded applications by partitioning their functionality in space and time-through a series of mutually-exclusive processing tasks synthesized multiplexed in time on the same set of resources-and achieving thus cost savings in both area and power metrics. However, the exploitation of this system versatility requires special attention to avoid performance degradation. Such technical aspects are addressed in this work intended to be a survey on reconfigurable hardware technology and aimed at defining an open, standard and cost-effective system architecture driven by flexible coprocessors instantiated on demand on reconfigurable resources of an FPGA. This concept fits well with the functional features demanded to many embedded applications today and its feasibility has been proved with a state-of-the-art commercial SRAM-based FPGA platform. The achieved results highlight dynamic partial reconfiguration as a potential technology to lead the next computing wave in the industry.

2007 IEEE International Parallel and Distributed Processing Symposium, 2007

Dynamically reconfigurable hardware allows for implementing systems that can be adapted at run-time according to the needs of the user. This paper presents an architecture that is composed of multiple FPGAs that are connected to an embedded processor. Thus, the architecture is referred to as a Multi-FPGA Clustered Architecture (MFCA). All FPGAs can be partially and dynamically reconfigured to integrate user-defined IP-Cores into the system at run-time. For the resource management and communication management we have implemented a Linux Operating System on the embedded processor that can be used to control the reconfiguration of the FPGAs by means of simple function calls. Furthermore, the Linux OS completely hides the physical infrastructure of the MFCA from user applications, offering a consistent interface to utilize partial reconfiguration. 1

The dynamically reconfigurable hardware can be changed during run-time and more areas of an application can be mapped to the hardware in sharing fashion with potential of parallel processing. This leads to an overall improvement in performance of reconfigurable FPGA fabric as the hardware accelerator . But the concurrence in sharing FPGA architecture is becoming an important issue. In this context, we develop a simple and intuitive algorithm to explain when and why a dynamic reconfiguration solution is lead to efficient and fair allocation of FPGA resource in sharing fashion. The operation volume increase or decrease policies are examined. We formulated a set of conditions that any increase or decrease policy should satisfy to ensure convergence to efficient and fair state in a distributed manner. Using the optimization considerations in convergence to fairness we showed that additive increase with multiplicative decrease of operation volume is the optimal policy.

IEEE Embedded Systems Letters, 2009

The dynamic partial reconfiguration technology enables an embedded system to adapt its hardware functionalities at run-time to changing environment conditions. However, reconfigurable hardware functions are still managed as conventional hardware devices, and the enhancement of system performance using the partial reconfiguration technology is thus still limited. To further raise the utilization of reconfigurable hardware designs, we propose a virtual hardware mechanism, including the logic virtualization and the hardware device virtualization, for dynamically partially reconfigurable systems. Using the logic virtualization technique, a hardware function that has been configured in the field-programmable gate array (FPGA) can be virtualized to support more than one software application at run-time. Using the hardware device virtualization, a software application can access two or more different hardware functions through the same device node. In a network security reconfigurable system for multimedia applications, our experimental results also demonstrate that the utilization of reconfigurable hardware functions can be further raised using the virtual hardware mechanism. Furthermore, the virtual hardware mechanism can also reduce up to 26% of the time required by using the conventional hardware reuse.

Garbage-Collection for reconfigurable hardware systems is another step to make dynamic reconfigurable hardware usable. By now, dynamic reconfiguration of FPGAs is still based on common hardware design concepts. This work describes a garbage-collector implementation for a reconfigurable hardware system, as part of a more dynamic hardware design concept. In this, the garbage-collector is an essential part of a flexible runtime system which considers reconfigurable modules as dynamic autonomous processing units. Different well-known garbagecollector schemes for software systems have been investigated to find the best solution for the already existing run-time system. A concurrent algorithm for garbage collection which uses a dedicated localized communication concept has been developed. Finally, a prove of concept has been done on the realized prototype. constraints of the "Module Based Design Flow". A similar layout can be found in [6], . Ullmann [8] applies an internal reconfiguration engine to this kind of structure avoiding an external host system for reconfiguration purposes.