Design issues of a multi-functional intelligent thermal test die

1993

A three dimensional (30) multichip module (MCM) using a silicon-on-silicon architecture has been constructed to evaluate the thermal performance of various design schemes. The module discussed in this paper has three planes of die, with each plane populated with four Assembly Test Chips (ATCs). Each chip has an array of 48 temperature sensing diodes which are used to map the temperature distribution across the chip surface. The design and construction of the module are discussed and the calibration of the diodes is reviewed. Experimental results are presented for the top suvace temperature distribution with the bottom substrate connected to a heat sink. These results are compared to those j-om a full pnite element calculation as well as to results using more approximate thermal analyss tools. 0-78030863-8/93/f3.00 01993 IEEE Ninth IEEE SEMI-THERMm Symposium

IEEE Transactions on Components and Packaging Technologies, 2009

Thermal measurement and modeling of multi-die packages with vertical (stacked) and lateral arrangement became a hot topic recently in different fields like RAM chip packaging or LEDs and LED assemblies. In our present study we present results for a more complex structure: an opto-coupler device with 4 chips in a combined lateral and vertical arrangement. The paper gives an overview of measurement and modeling techniques and results for stacked and MCM structures. It describes actual measurement results along with our structure function based methodology which helps validating the detailed model of the package being studied. Also, we show how one can derive junction-to-pin thermal resistances with a technique using structure functions.

… , IEEE Transactions on, 1998

Abstract— We report novel thermal characterization microstructures to measure the heat capacity of CMOS thin film sandwiches. This parameter is relevant, eg, for the dynamic response of thermal CMOS microtransducers and for the thermal management of integrated circuits. The test ...

2008 11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, 2008

This paper describes a systematic experimental and numerical study of the thermal characterization of a flip-chip package. A cold-plate based test method is used for thermal characterization and internal thermal resistance is used as the basis of all comparisons. Experiment results are presented for three flip-chip packages.

Microelectronic Test Structures ( …

No preference for poster or oral presentation Some process steps during wafer processing demand a carefully applied temperature budget. Novel test structures are presented for monitoring and determining this thermal budget during processing (such as sputtering or etching). Our system is based on well-defined silicidation reactions, simple to read out and enables an easy integration into existing layouts .

Proceedings of the IEEE, 2000

2006

Optimal package thermal design for today's high power processors is critical to meet demanding performance, cost, and reliability objectives. This paper describes the thermal characterization and development of the first generation CELL processor, developed jointly by Sony, Toshiba and IBM. The package not only provides the very high bandwidth necessary for electrical performance, but also achieves low thermal resistance to dissipate high power and maintain low die temperatures with superior reliability. The focus of the paper is the first level package. The target thermal resistance for the package is explained as determined from detailed 2nd level modeling and novel power map calculation and validation techniques are discussed. Thermal and mechanical modeling are used characterize the effects of the thermal interface material (TIM) on the thermal performance and mechanical response of the package. The thermal test strategy and the TIM characterization techniques are described. In summary, the paper describes the novel thermal modeling and characterization methodology used in the design process, allowing high heat flux in a low cost system application

Journal of Electronic Materials, 1989

Two-dimensional finite difference computer simulations were used for thermal analysis of an advanced multi-chip package design. In order to model high performance VLSI and ULSI applications, power dissipations ranging from 10 to 40 W/cm2 on each chip and zero to 5 W/cm2 on the substrate were simulated. It was found that heating due to resistive losses in the thin film interconnections between chips can impact package thermal performance. The calculated device-to-water thermal resistance was 0.4° C/W and the worst case chip-to-chip temperature variation was less than 22° C. This excellent thermal performance illustrates the effectiveness of the package’s water cooled heat sink with direct backside contact to each die. Methods to improve thermal performance are discussed.

Pm&r, 2004

In this paper measurement experiments prove that the structure function evaluation of the thermal transient testing is capable to locate die attach failure(s), even in case of stacked die packages. Both the strength and the location of the die attach failure may be determined with the methodology of a fast thermal transient measurement and the subsequent computer evaluation. The paper summarizes shortly the theoretical background of the method, and presents the use of the methodology with several measured examples. With the help of the presented correction procedure even the accurate values of the thermal layer parameters, such as thermal resistances or capacitances may be determined with the discussed thermal qualification methodology.

Microelectronics Journal, 2002

Silicon die surface temperature can be used to monitor the health state of digital and analogue integrated circuits (IC). In the present paper, four different sensing techniques: scanning thermal microscope, laser reflectometer, laser interferometer and electronic built-in differential temperature sensors are used to measure the temperature at the surface of the same IC containing heat sources (hot spots) that behave as faulty digital gates. The goal of the paper is to describe the techniques as well as to present the performances of these sensing methods for the detection and localisation of hot spots in an IC. q