Electrical Engineering

Blind deconvolution is presented in the underwater acoustic channel context, by time-frequency processing. The acoustic propagation environment was modelled as a multipath propagation channel. For noiseless simulated data, source signature estimation was performed by a model-based method. The channel estimate was obtained via a time-frequency formulation of the conventional matched-filter. Simulations used a ray-tracing physical model, initiated with at-sea recorded environmental data, in order to produce realistic underwater channel conditions. The quality of the estimates was 0.793 for the source signal, and close to 1 for the resolved amplitudes and time-delays of the impulse response. Time-frequency processing has proved to overcome the typical ill-conditioning of single sensor deterministic deconvolution techniques.

The requirement for rapid environmental assessment has motivated the development of prediction tools, which allow the observation and prediction in very short notice, of the ocean evolution in an interval up to 3–4 weeks, in given littoral areas. Complex systems exist nowadays, where multidimensional quantities like the oceanographic–biogeochemical–optical–acoustic fields, are tracked in time, melding measures and models of some or all the involved quantities. At some point in the prediction system, the acoustic forecast is computed by acoustic propagation models taking as input the environmental forecast. Inevitably, the error of the acoustic forecast as given by the model output, originates from at least two error sources. The first is the environmental forecast error. The second is due to the model inaccuracies, and to the dependence of propagation on parameters not dealt with by the prediction system, like geometric or geo-acoustic properties. The acoustic community has develope...

As IC technology scales down, interconnect issues are becoming one of the major concerns of gigahertz System-on-Chip (SoC) design. Voltage distortion (power supply noise) and delay violations (signal and clock skews) dramatically contribute to signal integrity loss. As a consequence, performance degradation, reliability problems and ultimately, functional error occur. In this paper, we propose a new methodology to enhance SoC signal integrity with respect to power/ground voltage transients, without degrading its performance. The underlying principle of the proposed methodology is to dynamically adapt the clock duty-cycle (CDC) according to the signal propagation delay through the logic whose power supply voltage is being disturbed. The methodology is based on architecture with a builtin power supply voltage sensor (BIPS), which monitors abnormal power grid activity, and a clock stretching logic (CSL) block, used to increase clock duty-cycle accordingly. Moreover, a model to accurately quantify CDC stretching as a function of V DD and/or Ground fluctuations is proposed. It is shown that the proposed methodology makes, for a set of valuable applications, the digital circuit more robust to power line fluctuations while maintaining at-speed clock rate. Moreover, when clock frequency reduction is inevitable, it enhances circuit tolerance when the disturbances start to occur, allowing the clock generator to react and reduce its frequency. This improves signal integrity when fast V DD disturbances occur. Experimental results based on SPICE simulations for simple combinational and pipeline circuits are used to demonstrate the assertions.

&SIGNAL INTEGRITY IS the ability of a signal to generate correct responses in a circuit. A signal with good integrity presents voltage values at required levels and level transitions at required times. For instance, a flip-flop with good signal integrity meets the setup and hold times. The loss of signal integrity results from effects that cause a circuit malfunction through distortion of the signal waveform. Researchers have studied various signal integrity problems in high-speed (gigahertz) nanometer-scale SoCs. The most relevant are the following: & crosstalk-signal distortion caused by crosscoupling effects between signals, 1 & overshoot/undershoot-signal momentarily rising or falling above or below the power supply voltage (V DD) and ground (V SS) lines, & reflection-echoing back a portion of a signal in high-frequency circuits with interconnections behaving as transmission lines, & electromagnetic interference resulting from antenna properties, 2 & power supply noise, 3 and & signal skew. 4 This article focuses on power supply disturbances, regardless of their origin, and their impact on digital-circuit performance. Both V DD depletion and ground elevation increase propagation delay in signal paths. The complexity of the problem increases when power management techniques that dynamically reduce V DD to minimize power consumption enter the picture. 5 These techniques are called dynamic voltage scaling (DVS). Proposed design solutions to enhance signal integrity in the presence of power grid activity include & 3D layout modeling and parasitic extraction, 6 & accurate RLC simulation of the on-chip power grid using decoupling capacitors to improve resistive voltage drop (IR drop), 3,4 & insertion of buffers on the grid, 6 and & shielding wires (for example, grounding every other line). 7 452 This article proposes a new methodology for enhancing SoC signal integrity without degrading performance in the presence of power-ground voltage transients. The underlying principle is the dynamic adaptation of the clock duty cycle to propagation delay variation along disturbed logic paths. This methodology makes digital circuits more robust to power line fluctuations while maintaining the at-speed clock rate.

In current CMOS nanometer technologies, aging effects may appear after relatively short operating times, compared to the expected lifetime of circuits. Therefore, there is an increasing need for on-chip aging monitoring, especially in high-performance, safety critical systems. This paper presents a programmable aging sensor that can be embedded in FPGAbased designs, using standard resources available in those devices and with minimal impact on the standard FPGA design flow. Given the limited amount of resources required by the sensor, it can be instantiated not only in the critical paths of a circuit, but also in those that may be identified to be more likely affected by aging effects. Experimental results, obtained in circuits of increasing complexity (where several sensors need to be used) are presented and discussed, demonstrating the good performance of the proposed sensor, as well as its low cost in terms of area overhead and power consumption. Results of aging experiments based on the standard US MIL-STD-883 Method 1015.50 "Burn-In Test" are also reported, demonstrating that the effect of aging on the sensor is negligible compared to that on the circuit under test, which is a key point for practical applicability. The proposed approach provides a novel and efficient solution to the specific FPGA design problems in this context, which are different from those addressed in ASIC design.

Several protocols have recently been defined for smart grids that enable the communication between electric devices and energy management systems. While these protocols and architectures can already be applied in different fields of micro grids, it is still not clear how the distributed resources and constraints of such electrical grids can be managed in an optimum way. In order to achieve a reduction in electricity costs and maximizing investments made in renewable sources, an optimization mechanism should be used to perform load scheduling, considering different variables such as forecasted power generation curve from renewable sources, different tariffs' rates, electric circuit constraints, user restrictions and correspondent comfort levels. Given these considerations, this work defines and evaluates a distributed micro grid resource management architecture and protocol which is able to optimize load scheduling while considering all the mentioned restrictions and parameters. The proposed architecture was implemented on a multi-agent simulator and the performed tests show that significant reductions in electricity cost can be achieved using this methodology. I.

The purpose of this paper is to present a new robust methodology for synchronous communications in a BUS, connecting multi-clock domains. Traditionally, when robust solutions are needed, an asynchronous communication is used. However, the low transfer rates associated with asynchronous solutions make them inadequate for high performance digital systems. On the other hand, synchronous communications do not guarantee dependability for all data, especially when different clock domains are interconnected. In this paper we propose to take advantage of these approaches, by combining, the robustness of asynchronous communication and the speed and simplicity of synchronous communications. A structure has been developed to implement the proposed communication approach. A test chip has been designed to implement that structure and prove the concept. The usefulness of the methodology is demonstrated in a complex FPGA data acquisition system. Simulation results are presented. I. INTRODUCTION The increasing communication data rates and the huge amount of data to be processed and transfer on present electronic systems put tremendous pressure on the communication architecture. Traditionally, two types of on-chip communication schemes have been considered, namely, point-to-point and bus-based communication architectures [1]. Point to point communication architectures can provide considerable communication performance at the expense of dedicated channels among all the communicating domains. On the other hand, bus-based architectures can connect a few tens of domains in a cost-efficient manner by reducing the design complexity and eliminating the dedicated wires required by point-to-point communication architectures.

As IC technology scales down, power supply instability may dramatically contribute to signal integrity loss. In this paper, we propose a new methodology to enhance circuit tolerance to powersupply voltage (V DD) local variations, without degrading its performance. The underlying idea is to add additional tolerance to the edge trigger of the clock signal driving specific memory cells. The clock duty-cycle (CDC) is thus dynamically modulated according to V DD. Two architectures are presented, and one of them is shown to be effective. The key module is a Clock Stretching Logic (CSL) block, used to increase CDC according to V DD-V SS variations. Moreover, when clock frequency reduction is inevitable, circuit tolerance when disturbances start to occur is enhanced, allowing the clock generator to react and reduce its frequency. Experimental results based on SPICE simulations for simple combinational, pipeline and finite-state machine (FSM) circuits are used to demonstrate the usefulness of the proposed methodology.

A new methodology is proposed to increase the robustness of pipeline-based circuits. The goal is to improve signal integrity in the presence of powersupply voltage (V DD) and/or temperature (T) variations, without degrading circuit performance. In the proposed methodology, we dynamically control the instant of data capture (the clock edge trigger) in key memory cells, according to local V DD and/or T variations. This way, data integrity lost is avoided, and circuit tolerance to power supply and/or temperature variations is enhanced. The methodology is based on a Dynamic Delay Buffer (DDB) block, used to sense V DD /T variations and to induce dynamic clock skews driving a limited subset of memory elements. Experimental results based on SPICE simulations for 2 sequential circuits are used to demonstrate that careful design may lead to improvements on circuit tolerance to V DD and/or T variations.

New product development using nanometer semiconductor technologies require high-quality BIST solutions able to uncover dynamic faults. Most existing solutions rely on test-per-scan BIST, for high fault coverage. However, reconfiguration, in test mode, may significantly modify delays in signal paths, thus reducing the degree of confidence of dynamic fault coverage values. The purpose of this paper is to present a new high-quality test-per-clock BIST methodology for sequential digital systems. The proposed BIST methodology is an extension to sequential systems of the masked-based (or m-BIST) methodology. Determinism in test patterns (to uncover randompattern resistant faults) is inserted with a low-intrusion scheme, in which the sequential behavior is preserved, and a bit-flipping technique is used. Functional-oriented patterns lead to high coverage of structural faults. Both academic (VeriDOS, ASCOPA) and commercial (Design_Vision™, Verifault™) tools are used to implement the methodology, which is demonstrated with an industrial design, the PIC controller of an electric static power meter. The methodology has been incorporated in the industrial partner design flow.

The work developed consists in a power or performance optimization methodology, for long-term operation, using global and local aging aware performance sensors. Methodology allows circuits to be dynamically optimized, during their lifetime , according with one of two possible needs: (1) restrict power consumption, by reducing power-supply voltage to the minimum value that prevents errors from happening; or (2) optimize performance, by increasing operating frequency to the maximum limit that prevents errors' occurrence. The dynamic optimization is achieved by using a cooperative work of global and local sensors. Moreover, new global sensor architecture, controller and a DCO (Digital Control Oscillator) are presented, to demonstrate frequency automatic optimization, according with sensors' outputs. Extensive spice simulations in a 65nm CMOS technology demonstrate the results.

Product development economics and specs drive the need for on chip embedded test functionality. However, optimal partitioning of test functionality between a tester and a SOC is a non-trivial task, which must be solved during the system analysis phase. Hence, at system level, a trade-off analysis must be performed, in order to evaluate the costs and benefits of different partitioning schemes. The purpose of this contribution is to present a methodology and tools, using the Object Oriented (OO) Paradigm and UML, and a set of architectural Quality Metrics (QMs), to analyze the impact of different TRP schemes on system's architecture. A 4-core SOC case study is presented to guide the discussion.

As IC technology scales down, interconnect issues are becoming one of the major concerns of gigahertz Systemon-Chip (SoC) design. Voltage distortion (power supply noise) and delay violations (signal and clock skews) dramatically contribute to signal integrity loss. As a consequence, performance degradation, reliability problems and ultimately, functional error occur. In this paper, we propose a new methodology to enhance SoC signal integrity with respect to power/ground voltage transients, without degrading its performance. The underlying principle of the proposed methodology is to dynamically adapt the clock duty-cycle (CDC) according to the signal propagation delay through the logic whose power supply voltage is being disturbed. The methodology is based on architecture with a built-in power supply voltage sensor (BIPS), which monitors abnormal power grid activity, and a clock stretching logic (CSL) block, used to increase clock duty-cycle accordingly. Moreover, a model to accurately quantify CDC stretching as a function of V DD and/or Ground fluctuations is proposed. It is shown that the proposed methodology makes, for a set of valuable applications, the digital circuit more robust to power line fluctuations while maintaining at-speed clock rate. Moreover, when clock frequency reduction is inevitable, it enhances circuit tolerance when the disturbances start to occur, allowing the clock generator to react and reduce its frequency. This improves signal integrity when fast V DD disturbances occur. Practical experiments based on FPGA implementation for a simple benchmark circuit were performed to demonstrate the assertions.

In emerging nanometer semiconductor technologies, physical defects detection is a challenge. Three parameters can be used to enhance the panoply of test techniques: clock frequency (f MAX), power supply voltage (V DD) and temperature (T). However, their impact on system performance needs to be computed, in order to develop new test and DfT techniques. The purpose of this paper is to introduce a semi-empirical analytical model to compute, at logic level, the impact of V DD variations (∆V DD) and/or temperature variations (∆T) on the variation of the maximum clock frequency of operation (∆f MAX) of a digital module. The proposed model computes the dependence of propagation delay variations of logic elements (∆t pd) and signal paths (∆T pd) on ∆V DD and ∆T. Moreover, a duality becomes visible. In fact, a given ∆T pd (or f MAX) variation can be injected either by a given ∆V DDi variation, or by a given ∆T j variation. This duality can be exploited to increase test effectiveness in a production or lifetime test environment. The model is backannotated to logic level, to allow low-cost fault simulation. The availability, on chip, of multiple V DD values in products with DVS (Dynamic Voltage Scaling), such as large microprocessors, will open new opportunities for novel built-in test techniques using multi-frequency, multi-V DD and multi-temperature schemes.

This paper presents a new aging sensor architecture for error prediction of performance errors in synchronous digital circuits. The aging sensor is based on a new flip-flop with built-in logic that predicts the errors by monitoring long-term performance degradation of CMOS digital systems. The main advantage is that the sensor's long-term degradation effects increase its sensitivity to performance error prediction. Moreover, the reduction of the power-supply voltage (V) and the increase of the temperature (T) also make the sensor to increase its sensitivity, making the sensor to adapt its monitoring capability with aging and VT variations. Performance failure prediction is implemented by the detection of late transitions at flip-flop data input, caused by aging (namely, due to NBTI), or to physical defects activated by long lifetime operation, or even by a worst-case operating condition (namely, V and/or T). Extensive SPICE simulations allowed achieving a new flip-flop with additional aging sensor capability, however with negligible performance degradation, because the sensing circuitry is out of the signal path. Simulation results are presented for two CMOS technologies (65nm and 22nm), using Berkeley Predictive Technology Models (PTM). It is shown that PVTA (Process, power supply Voltage, Temperature and Aging) variations on the sensor enhance error prediction capability.

Detection of physical defects in nanometer electronic products requires the detection of dynamic faults. Parametric test, using variable power supply voltage, V DD , can prove to be rewarding. Usually, parametric self-test, namely during product lifetime, is not cost-effective. However, on-chip availability of multiple V DD values in products with Dynamic Voltage Scaling (DVS) opens opportunities for novel BIST techniques using multi-V DD techniques, which can be used for production and lifetime test. The purpose of this paper is to demonstrate that physical defects, inducing delay faults in critical paths or in short paths (small-delay defects), can be detected using a classic BIST architecture and a multi-V DD scheme. Performance violations for different V DD values are captured in digital signatures, which significantly differ from the faultfree signature. Both resistive open and bridging defects are detectable by the proposed scheme. As both the circuit under test and the BIST circuitry are under V DD variations, corrupted signatures may emerge due to abnormal behaviour from these two sources. Simulation results are shown with an industrial design, XTRAN (a fleet management system) from Tecmic, and two CMOS technologies.

The Mobile Five Senses Augmented Reality System for Museums (M5SAR) project aims to development an Augmented Reality mobile system for museums. Museums are amazing places, where it is important to sensorial augment as much as possible the visits, permitting to see, ear, touch, smell, and taste all the interesting objects there exist. Also fundamental is that visitors with different profiles (child, adult, expert, etc.) can have different experiences when visiting the same object. In the M5SAR system, the visitor uses its smartphone to select the object(s) to explore, and the user interface adapts on-the-fly to the object(s) and user's profile. Simultaneously, when integrated, a paired hardware device allows the extension of the augmented reality system to the human five senses, complementing the visual and auditory information about the objects. This chapter presents the initial framework to develop a five senses mobile adaptive museum system.

Bipolar DC grids have become an adequate solution for high-power microgrids. This is mainly due to the fact that this configuration has a greater power transmission capacity. In bipolar DC grids, any distributed generation system can be connected through DC-DC converters, which must have a monopolar input and a bipolar output. In this paper, a DC-DC converter based on the combination of single-ended primary-inductor converter (SEPIC) and Ćuk converters is proposed, to connect a photovoltaic (PV) system to a bipolar DC grid. This topology has, as main advantages, a reduced number of components and a high efficiency. Furthermore, it can contribute to regulate/balance voltage in bipolar DC grids. To control the proposed converter, any of the techniques described in the literature and applied to converters of a single input and single output can be used. An experimental prototype of a DC-DC converter with bipolar output based on the combination of SEPIC and Ćuk converters was developed....

In many countries, renewable energy production already represents an important percentage of the total energy that is generated in electrical grids. In order to reach higher levels of integration, demand side management measures are yet required. In fact, different from the legacy electrical grids, where at any given instant the generation levels are adjusted to meet the demand, when using renewable energy sources, the demand must be adapted in accordance with the generation levels, since these cannot be controlled. In order to alleviate users from the burden of individual control of each appliance, energy management systems (EMSs) have to be developed to both monitor the generation and consumption patterns and to control electrical appliances. In this context, the main contribution of this chapter is to present the implementation of such an IoT-based monitoring and control system for microgrids, capable of supporting the development of an EMS.