Time-domain PLL modeling and RJ/DJ jitter decomposition
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016
Bit rates of high speed serial links (USB, SATA, PCI-express, etc.) have reached the multi-gigabi... more Bit rates of high speed serial links (USB, SATA, PCI-express, etc.) have reached the multi-gigabits per second, and continue to increase. Two of the major electrical parameters used to characterize SerDes Integrated Circuit performance are the transmitted jitter at a given bit error rate (BER) and the receiver capacity to track jitter at a given BER. Modeling the phase noise of the different SerDes components, extracting the time jitter and decomposing it, would help designers to achieve desired Figure of Merit (FoM) for future SerDes versions. The phase locked loop (PLL) is one of the contributors of clock random and periodic jitter inside the system [1]. This paper presents a method for modeling the PLL with phase noise injection and estimating the time domain jitter. A time domain model including PLL loop nonlinearities is created in order to estimate jitter. The Standard Organizations specify random and deterministic jitter budgets. In order to decompose the PLL output jitter, a new technique for jitter analysis and decomposition is proposed. Modeling simulation results correlate well with measurements and this technique will help designers properly identify and quantify the sources of deterministic jitter and their impact on the SerDes system.
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Papers by nabil houdali