Frontier research center

The electrical characteristics of In 0.18 Al 0.82 N/GaN MOSHEMTs-on-Si (111) with Y 2 O 3 gate dielectric of thickness between 5 to 30 nm are reported. A positive shift in threshold voltage, V th , with respect to Schottky gate HEMTs is observed, which is in contrast to that for ZrO 2 gate dielectric MOSHEMTs. An analytical V th model is proposed to quantify the fixed oxide charges at the Y 2 O 3 /In 0.18 Al 0.82 N interface (n ox,intf ) and in the Y 2 O 3 bulk (n ox,bulk ). The negative polarity of the fixed oxide charges (n ox,intf , n ox,bulk ) is believed to be the reason for the abovementioned positive V th shift. X-ray photoelectron spectroscopy analysis reveals that a thin interfacial layer (IL) may have formed as a result of spontaneous reaction between dielectric Y 2 O 3 and In 0.18 Al 0.82 N/GaN heterostructure, leaving Y 2 O 3 bulk on top for thick dielectric film. We believe n ox,intf is located in the IL and that its polarity and magnitude are related to the constituents of the IL, which comprise mainly YAlO x N y and its sub-oxynitrides. It is also observed that Y 2 O 3 bulk has negative fixed charges (n ox,bulk ) with a magnitude that depends on film densification upon thermal annealing treatment.

Dynamic backlight scaling (DBS), a technique for LCD power reduction, often deteriorates image quality because of a flicker (unintended temporal variation of the luminance) generated in the frame at which the backlight level changes. This paper proposes a novel DBS algorithm to reduce the flicker by decreasing the quantization errors (QEs) that are created in the multiplication of the input gray level and the DBS scaling ratio as well as in the mapping of the multiplication result to an integer gray level. The proposed DBS algorithm reduces the QE down to 28.8% when compared with the conventional DBS algorithm.

The use of high quality strained-silicon (strained-Si) layers grown on relaxed-SiGe substrates or on an insulator holds a great promise to enhance conventional Si complementary metaloxide-semiconductor (Si-CMOS) technology. In order to fabricate MOSFETs on a Si substrate, conventionally a very thin layer of insulator is thermally grown or deposited on the Si substrate followed by a poly-silicon gate electrode definition. To enhance the reliability of ultra thin dielectrics required for MOS devices, films with low leakage current, improved charge trapping character-istics and high dielectric strength are necessary. It has been shown that strained-Si on SiGe layers is stable with respect to high temperature processing steps (with no mobility reduction for thermal treatments) up to only 800 8C for 30 min and 950 8C for 3 min . Low thermal budget processing, such as, rapid thermal oxidation (RTO) is thus essential. Rapid thermal oxidation of strained-Si is particularly attractive for the minimization of thermal budget to avoid strain relaxation in heterolayers . In addition, RTO offers better control over oxide growth in the thin oxide regime compared to furnace oxidation and plays an important role in present day IC-manufacturing. As the oxidation kinetics of strained-Si is different from oxidation of conventional bulk-Si, hence detail study is needed further. In this work, we report, for the first time, the results of internal photoemission (IPE) study on charge trapping in rapid thermal oxides (5-7 nm) grown at several oxidation temperatures between 650 and 950 8C for 90 s on strained-Si/Si 0.8 Ge 0.2 heterolayers and

Effects of annealing on surface-activated bonding (SAB)-based Si/Si junctions were investigated by transmission electron microscopy (TEM) observations and current-voltage (I-V) measurements. We observed an amorphous-like layer at the bonding interface, which was recrystallized by annealing. We extracted the potential barrier heights at Si/Si interfaces annealed at different temperatures from the results of I-V measurements at various ambient temperatures. For p-Si/p-Si junctions, the barrier height increased as the annealing temperature increased from 200 to 400°C and decreased from 400 to 1000°C. For n-Si/n-Si junctions, the barrier height increased as the annealing temperature increased from 200 to 600°C and decreased from 600 to 1000°C. By using the charge neutral level (CNL) model, we estimated the energy of CNL, E CNL , and the density of interface states, D it , at each annealing temperature. D it decreased as the annealing temperature increased from 400 to 1000°C. E CNL showed values larger than the reported ones.

The change in the morphology of various gate dielectrics (including deposited ZrO 2 and TiO 2) on strained-Si on relaxed SiGe/Si and strained-SiGe layers is studied using an atomic force microscope (AFM). The AFM observation was carried out before and after oxidation. It has been found that the oxidation rate of strained-Si was affected by the existence of the crosshatch related surface morphology. As a result, the surface roughness increases after oxidation. The roughness increase is more pronounced in a 26% Ge-content samples than in a 9% Ge-content sample. Transmission electron microscopy (TEM) has been used to identify the structure of the deposited layers and their interface with the strained-Si or SiGe substrates. Structural and electrical characterization results for deposited high-k gate dielectrics on strained-Si using Al/ZrO 2 /n-Si and Al/TiO 2 / n-Si metal-insulator-semiconductor (MIS) structures with equivalent oxide thickness (EOT) of 2.5 nm are presented. Effects of nitrogen incorporation on the electrical, interfacial, charge trapping and reliability properties of ultrathin oxide/oxynitride films grown using rapid thermal oxidation on strained-SiGe substrates are also discussed.

The authors have studied the electrical characteristics of Hf/Al/Ta ohmic contacts on In 0.18 Al 0.82 N/GaN heterostructure grown on Si (111) substrate. With annealing at 600 C in vacuum (which is $200 C lower than that for traditional Ti/Al/Ni/Au contacts), a minimum ohmic contact resistance of $0.58 XÁmm and specific contact resistivity of $6.75 Â 10 À6 XÁcm 2 are obtained. The minimum contact resistance of Hf/Al/Ta contacts is comparable to that of Ti/Al/Ni/Au contacts. Owing to the lower annealing temperature, Hf/Al/Ta contacts exhibit better surface morphology and edge acuity. More importantly, Hf/Al/Ta contacts show a smooth interface with In 0.18 Al 0.82 N/GaN, whereas spike structures that penetrate the In 0.18 Al 0.82 N layer are observed for Ti/Al/Ni/Au contacts. As a result, the source-carrier-injection induced breakdown mechanism is reduced in the In 0.18 Al 0.82 N/GaN-on-Si high electron mobility transistors (HEMTs) with Hf/Al/Ta ohmic contacts, thereby leading to an improved three-terminal off-state breakdown voltage by about 100 V

The reliability characteristics of SiO 2 /ZrO 2 gate dielectric stacks on strained-Si/Si 0.8 Ge 0.2 have been investigated under dynamic and pulsed voltage stresses of different amplitude and frequency in order to analyze the transient response and the degradation of oxide as a function of stress parameters. The current transients observed in dynamic voltage stresses have been interpreted in terms of the charging/discharging of interface and bulk traps. The evolution of the current during unipolar pulsed voltage stresses shows the degradation being much faster at low frequencies than at high frequencies. Results have been compared with those obtained after CVS, as a function of injected charge and pulse frequency.

The trapping/detrapping behavior of charge carriers in ultrathin SiO 2 /TiO 2 stacked gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Titanium tetrakis iso-propoxides (TTIP) was used as the organometallic source for the deposition of ultra-thin TiO 2 films at low temperature (o200 1C) on strained-Si/relaxed-Si 0.8 Ge 0.2 heterolayers by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. Stress-induced leakage current (SILC) through SiO 2 /TiO 2 stacked gate dielectric is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of TiO 2 layer. The increase in the gate current density observed during CVS from room temperature up to 125 o C has been analyzed and modeled considering both the buildup of charges in the layer as well as the SILC contribution. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of $10 À19 cm 2 as compared to $10 À16 cm 2 in SiO 2 has been observed. A temperature-dependent trap generation rate and defects have also been investigated using time-dependent current density variation during CVS. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating high-k stacked layers. SILC generation kinetics, i.e. defect generation probability under different injected fluences for various high-constant stress voltages in both polarities have been studied. An empirical relation between trap generation probability and applied stress voltage for various injected fluences has been developed.

Potential of high-k dielectric films for future scaled charge storage non-volatile memory (NVM) device applications is discussed. To overcome the problems of charge loss encountered in conventional flash memories with silicon-nitride (Si 3 N 4) films and polysilicon-oxide-nitride-oxide-silicon (SONOS) and nonuniformity issues in nanocrystal memories (NC), such as Si, Ge and metal, it is shown that the use of highk dielectrics allows more aggressive scaling of the tunnel dielectric, smaller operating voltage, better endurance, and faster program/erase speeds. Charge-trapping characteristics of high-k AlN films with SiO 2 as a blocking oxide in p-Si/SiO 2 /AlN/SiO 2 /poly-silicon (SOHOS) memory structures have been investigated in detail. The experimental results of program/erase characteristics obtained as the functions of gate bias voltage and pulse width are presented.

TaYO x-based metal-insulator-metal (MIM) capacitors with excellent electrical properties have been fabricated. Ultra-thin TaYO x films in the thickness range of 15-30 nm (EOT $ 2.4-4.7 nm) were deposited on Au/SiO 2 (100 nm)/Si (100) structures by rf-magnetron co-sputtering of Ta 2 O 5 and Y 2 O 3 targets. TaYO x layers were characterized by X-ray photoelectron spectroscopy (XPS), energy dispersive X-ray (EDX) and Xray diffraction (XRD) to examine the composition and crystallinity. An atomic percentage of Ta:Y = 58.32:41.67 was confirmed from the EDX analysis while XRD revealed an amorphous phase (up to 500°C) during rapid thermal annealing. Besides, a high capacitance density of $3.7-5.4 fF/lm 2 at 10 kHz (e r $ 21), a low value of VCC (voltage coefficients of capacitance, a and b) have been achieved. Also, a highly stable temperature coefficient of capacitance, TCC has been obtained. Capacitance degradation phenomena in TaYO x-based MIM capacitors under constant current stressing (CCS at 20 nA) have been studied. It is observed that degradation depends strongly on the dielectric thickness and a dielectric breakdown voltage of 3-5 MV/cm was found for TaYO x films. The maximum energy storage density was estimated to be $5.69 J/cm 3. Post deposition annealing (PDA) in O 2 ambient at 400°C has been performed and further improvement in device reliability and electrical performances has been achieved.

In this work, we present the results of dielectric relaxation and defect generation kinetics towards reliability assessments for Zr-based high-k gate dielectrics on p-Ge (1 0 0). Zirconium tetratert butoxide (ZTB) was used as an organometallic source for the deposition of ultra thin ($14 nm) ZrO 2 films on p-Ge (1 0 0) substrates. It is observed that the presence of an ultra thin lossy GeO x interfacial layer between the deposited high-k film and the substrate, results in frequency dependent capacitance-voltage (C-V) characteristics and a high interface state density ($10 12 cm À2 eV À1). Use of nitrogen engineering to convert the lossy GeO x interfacial layer to its oxynitride is found to improve the electrical properties. Magnetic resonance studies have been performed to study the chemical nature of electrically active defects responsible for trapping and reliability concerns in high-k/Ge systems. The effect of transient response and dielectric relaxation in nitridation processes has been investigated under high voltage pulse stressing. The stress-induced trap charge density and its spatial distribution are reported. Charge trapping/ detrapping of stacked layers under dynamic current stresses was studied under different fluences (À10 mA cm À2 to À50 mA cm À2). Charge trapping characteristics of MIS structures (Al/ZrO 2 /GeO x /Ge and Al/ZrO 2 /GeO x N y /Ge) have been investigated by applying pulsed unipolar (peak value-10 V) stress having 50% duty-cycle square voltage wave (1 Hz-10 kHz) to the gate electrode.

The potential usage of thermally robust RuO x Schottky contacts in III-nitride-based Schottky diodes and high electron mobility transistors (HEMTs) has been investigated. RuO x is deposited on nitride surface by sputtering Ru in Ar/O 2 ambient. The influence of post sputtering annealing ambient and temperature on the characteristics of RuO x Schottky diodes on n-type GaN on Si(111) substrate is addressed. We also report the comparative study of thermal stability between RuO x and Ni/Au Schottky diodes on In x Al 1-x N/GaN on Si(111) substrate in terms of the reverse bias leakage current and Schottky barrier height (SBH). RuO x contact shows a higher SBH of 1.24 eV and a lower leakage current of ~10-5 Acm-2 (~four orders of magnitude lower than that of Ni/Au) on In x Al 1-x N/GaN at-40 V after annealing at 800 o C in N 2. In addition, RuO x Schottky gate HEMT on In x Al 1-x N/GaN on Si(111) substrate has shown a low gate leakage current of ~6×10-8 A/mm at-8 V after annealing at 700 o C in N 2 for 1 minute. The lower gate leakage current has resulted in a transistor ON/OFF current ratio of ~10 5. The maximum transconductance and ON-resistance achieved by such HEMTs are about 0.18 S/mm and 8.33 Ωmm, respectively, for a gate length of 1.5 µm.

In this work, we present the results of physical and electrical characterization of Ti-based high-k gate dielectrics on Ge substrates. Titanium tetrakis isopropoxide (TTIP) was used as the organometallic source for the deposition of ultra-thin TiO 2 films on p-Ge (1 0 0) at low temperature (<200 • C) by plasma enhanced chemical vapor deposition (PECVD) technique in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of ∼65 Pa. The presence of an ultra-thin lossy GeO 2 interfacial layer between the deposited high-k film and the substrate, results in frequency-dependent capacitance-voltage (C-V) characteristics in strong accumulation and a high interface state density (∼10 13 cm −2 eV −1). To improve the electrical properties, nitrogen engineering has been employed to convert the lossy GeO 2 interfacial layer to its oxynitride, thus forming TiO 2 /GeO x N y /Ge stacked-gate structure with improved interface/electrical properties. Different N sources, such as NO, NH 3 and NO/NH 3 , have been used for nitrogen engineering. XPS and Raman spectroscopy analyses have been used for surface morphological study. Electrical properties, such as gate leakage current density, interface state density, charge trapping, flatband voltage shift, etc, have been studied in detail for TiO 2 /GeO x N y /Ge MIS capacitors using the current-voltage (I-V), capacitance-voltage (C-V), conductance-voltage (G-V) and stress (both constant voltage and current) measurements. Although a significant improvement in electrical characteristics has been observed after nitridation in general, the formation of the interfacial GeO x N y layer, obtained from NO-plasma nitridation, is found to provide the maximum improvement among all the nitridation techniques used in this study. It is shown that the insertion of an ultra-thin oxynitride (GeO x N y) interfacial layer is advantageous for producing gate-quality TiO 2 high-k dielectric stacks on Ge substrates.

The results of a comparative study on the charge trapping/detrapping behavior in thin ZrO 2 and TiO 2 high-k gate dielectrics on p-Ge (100) under stressing in constant current (CCS, 1.02-5.1 C cm − 2) and voltage (CVS, −5 V to −7 V) at gate injection mode are presented. Stoichiometric thin films of ZrO 2 and TiO 2 have been deposited on p-Ge (100) using organometallic sources at relatively low temperature (b200°C) by plasma enhanced chemical vapor deposition (PECVD) technique in a microwave (700 W, 2.45 GHz) plasma discharge at a pressure of 66.67 Pa. The effect of stressing on several important interfacial parameters, like, interface state density, fixed oxide charge, oxide charge centroids, and capture cross-section of traps etc. is reported.

Current imaging tunneling spectrum obtained from scanning tunneling microscopy has been used to probe the formation and/or rupture of conductive filaments responsible for bipolar switching in Pd nano-dots embedded Nb 2 O 5 memristors. Filamentary conduction mechanism has been confirmed by scanning tunneling microscopy study using a Pt-Ir tip that enabled performing electroforming and reset operations at the nanoscale. The back and forth transition between the fully oxidized and metallic sub-oxide states of niobium under applied bias, as observed from X-ray photoelectron spectroscopy, is believed to be the source of bipolar switching in Nb 2 O 5 memristors. The incorporation of Pd nanodots in Nb 2 O 5 matrix plays a critical role by acting as an oxygen ion reservoir and/or by polarizing a large volume of oxygen vacancies. The formation and/or rupture of the conducting filaments through trapping-detrapping phenomena are found to boost the memristive switching performance.

The mechanisms of ohmic contact formation and carrier transport of low temperature (600 • C) annealed Hf/Al/Ta on In 0.18 Al 0.82 N/GaN heterostructure grown on Si substrate have been investigated. The Hf/Al/Ta ohmic contacts have a smooth interface with In 0.18 Al 0.82 N/GaN, and the formations of HfN and Hf-Al alloy near the metal-semiconductor interface are critical to achieving good ohmic contact. Thermionic field emission (TFE) is found to be the dominant carrier transport mechanism in the Hf/Al/Ta ohmic contacts on In 0.18 Al 0.82 N/GaN and analysis of the TFE model has revealed a high carrier density of 1.72 × 10 19 cm −3 and an effective barrier height of 0.48 eV. The sheet resistance of the In 0.18 Al 0.82 N/GaN substrate is shown to increase with temperature by the power-law (∝ T 1.55). A series two-barrier model has been used to explain the carrier transport through the Hf/Al/Ta ohmic contacts on In 0.18 Al 0.82 N/GaN with a smooth metal-semiconductor interface. It has also been shown that the Hf/Al/Ta contacts on In 0.18 Al 0.82 N/GaN are stable at 350 • C in air for more than 200 hours.

Internal photoemission and magnetic resonance studies have been performed to investigate the charge trapping kinetics and chemical nature of defects present in ultrathin high-k dielectric films deposited on p-Ge (100) substrate. Both the band and defect-related electron states were characterized through EPR, IPE, C-V and I-V measurements under UV-illumination. The interface trap spectrum in Ge/high-k oxide systems appears to be dominated by slow acceptor states with a broad energy distribution as major contribution comes from the imperfections located in the insulating layer. However, the oxynitride samples demonstrate lower defect or trapping behavior over non-nitrided samples.

The feasibility of YTiO x as a high-k gate dielectric for germaniummetal-oxide-semiconductor (MOS) devices has been investigated. The effects of different concentration of TiO x on electrical properties of YTiO x-based MOS capacitors are reported. It has been demonstrated that higher TiO x concentration in YTiO x may help to boost up dielectric constant while it causes serious damage to the interfacial properties. It has been observed that YTiO x film can effectively prevent re-growth of GeO x-based interfacial layer likely due to formation of stable Y-Ti-germanate at the interface in consequence of strong interaction of YTiO x with underlying Ge substrate. Indeed, YTiO x with 22% TiO x exhibits fairly good electrical characteristics with high dielectric constant value of κ~21±1. The potentiality of YTiO x has further been examined with gate oxide downscaling and the results are compared with that of regularly used high-κ dielectrics promising for Ge MOSFETs.

The electrical performance of both Ge MOSCAP and MOSFET with LaScOx high-k gate dielectric directly deposited on Ge (100) without utilizing any interfacial passivation layer has been investigated. This study also reports about the control of Vfb/Vth through ScO concentration. Accordingly, a relatively larger hysteresis and higher density of interface states with ScO concentration having lower or higher than 50% along with increasing annealing temperatures were observed in general as a result of deterioration caused by the formation of GeOx at the interface in conjunction with more pronounce intermixing or Ge out-diffusion into LaScOx. Nevertheless, an ultrathin Si passivation layer is found to be advantageous to inhibit Ge incorporation into high-k bulk in the form of GeOx, thereby diminishing the resultant oxide charge trapping as well as improves the thermal stabilities of the entire LaScOx/Ge MOS structures. Besides, reasonably good electrical properties of Ge p-MOSFETs with LaSc...