Department of Public Relations and Communications

Cellular neural network (CNN) implementations used in real time image processing are rapidly generated by a formal High-level synthesis (HLS) toolset in this work. Industrial and academic hardware design projects can benefit from the use of the Custom Coprocessors Compilation (CCC) HLS behavioral synthesise, via the massive reduction in design and verification time. The CCC tool is built with formal compiler-compiler, Logic Programming and XML validation techniques, thus the generated RTL VHDL or Verilog models are provably-correct. In this work, we rapidly modeled CNNs in the ADA programming language, compiled and verified along with all the necessary testbenches in GNU ADA. Edge-detection, halftoning and morphological processing applications were prototyped, so as to evaluate the CCC HLS method, which was the main contribution of this work. The combination of Logic Programming and RDF validation techniques, as well as prototyping of CNN applications made this work unique.

In this contribution, behavioral synthesis tools are used for hardware implementation of a cellular neural network with the ability to accomplish image processing tasks in real time. Behavioral synthesis tools such as the CCC HLS framework can deliver correct-by-construction RTL VHDL implementations of computation-intensive applications such as image processing and cellular neural networks. The tool applies formal techniques to transform behavioral ADA specifications into RTL micro-architectures which then can be easily implemented by commercial RTL synthesizers. Example applications such as, edge-detection, halftoning and morphological operations, validate the presented contribution.

An integrated, formal high-Level synthesis (HLS) framework is used in this work for hardware implementation of cellular neural networks, which are used in real time image processing. The Custom Coprocessors Compilation (CCC) HLS behavioral synthesiser generates correct-by-construction register transferlevel (RTL) VHDL hardware models of computation-intensive applications. Thus, time-consuming RTL and gate-level simulations are avoided and verification time is cut down to a fraction of the usual time that takes to achieve the same goal with traditional approaches. Such applications include image processing with cellular neural networks (CNNs). The synthesizer utilizes formal compiler-compiler and logic programming techniques, to transform algorithmic ADA into RTL VHDL or Verilog which are directly implementable into hardware using any available RTL synthesizer. The CNNs were rapidly coded, compiled and verified along with all the necessary testbenches in GNU ADA. The applications targeted here are edge-detection, halftoning and morphological processing, which are used to evaluate the CCC HLS framework. The contribution of this work is hardware implementation of CNNs using the CCC HLS tools to formally, and rapidly develop, verify and prototype advanced image processing applications.

In this paper, an existing method for detection of geometric active contours is discussed. The method examines functionals that depend on the curve geometry and image properties in a level-set framework. More specifically, the cost function that is sought to be minimized is formulated as a weighted sum of three integral measures; a robust alignment term that leads the evolving surface to the edges of the desired object, a minimal variance term that measures the homogeneity inside and outside the object, and a geodesic active surface term that is used mainly for regularization. The algorithm is implemented in MatLab, ADA and subsequently, it was ported to a behavioral synthesis tool, the CCC HLS framework in order to deliver correct-by-construction RTL VHDL implementations of computation-intensive applications. This way, behavioral ADA specifications are transformed into RTL micro-architectures which then can be easily implemented by commercial RTL synthesizers. The designs were verified rapidly at the MatLab and compiled ADA code level, as well as RTL-level simulations were executed to prove the argument of the correctness at the level of the automatically generated RTL VHDL implementations.