Sherwani, 1995 - Google Patents

VLSI physical design automation

Sherwani, 1995

Document ID
13688055273130656079
Author
Sherwani N
Publication year
Publication venue
Algorithms for VLSI Physical Design Automation

External Links

Snippet

Integrated Circuit (IC) has transformed our society into an information society. It. impacts all walks of life and promises to be even more dominating with the arrival of information superhighway. This revolutionary development and widespread use of Ies has been one of …
Continue reading at link.springer.com (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5077Routing
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081Layout analysis, e.g. layout verification, design rule check
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/5054Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5072Floorplanning, e.g. partitioning, placement
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/505Logic synthesis, e.g. technology mapping, optimisation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5036Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5022Logic simulation, e.g. for logic circuit operation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78Power analysis and optimization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70Fault tolerant, i.e. transient fault suppression
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled

Similar Documents

Publication Publication Date Title
US6240542B1 (en) Poly routing for chip interconnects with minimal impact on chip performance
Sait et al. VLSI physical design automation: theory and practice
Trimberger Field-programmable gate array technology
Vai VLSI design
Kahng et al. VLSI physical design: from graph partitioning to timing closure
US8037441B2 (en) Gridded-router based wiring on a non-gridded library
Sarrafzadeh et al. Modern placement techniques
US6247164B1 (en) Configurable hardware system implementing Boolean Satisfiability and method thereof
US7865855B2 (en) Method and system for generating a layout for an integrated electronic circuit
US7159202B2 (en) Methods, apparatus and computer program products for generating selective netlists that include interconnection influences at pre-layout and post-layout design stages
US6360350B1 (en) Method and system for performing circuit analysis on an integrated-circuit design having design data available in different forms
JP2002110797A (en) Method for designing clock wiring
US6820048B1 (en) 4 point derating scheme for propagation delay and setup/hold time computation
Sengupta Design flow of a digital IC: the role of digital IC\/SOC design in CE products
Kanase et al. Physical implementation of shift register with respect to timing and dynamic drop
Minz et al. Block-level 3-D global routing with an application to 3-D packaging
US20040003363A1 (en) Integrated circuit design and manufacture utilizing layers having a predetermined layout
US7117467B2 (en) Methods for optimizing package and silicon co-design of integrated circuit
Sherwani VLSI physical design automation
US20060085778A1 (en) Automatic addition of power connections to chip power
Preas et al. Automatic layout of silicon-on-silicon hybrid packages
Donze et al. Masterimage approach to VLSI design
Shohal et al. Efficient RTL to GDS II Flow for Finite State Machine Integration: A Physical Design Approach
EP1650688A1 (en) Automatic addition of power connections to chip power supply network
Carrig et al. A clock methodology for high-performance microprocessors