TWI462116B - 3d memory array with improved ssl and bl contact layout - Google Patents

Description

Three-dimensional memory array with improved tandem select line and bit line contact layout

This invention relates to high density memory devices, and more particularly to memory devices having multiple layers of planar memory cells to provide a three dimensional array.

When the critical size of the device in the integrated circuit is reduced to the limit of the usual memory cell technology, the designer turns to the memory cell multi-stack plane technology to achieve higher storage density and lower cost per bit. . For example, thin film transistor technology has been applied to charge trapping memory, see the paper "A multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory", IEEE Int'l Electron Device Meeting, December 11-13, 2006; and Jung et al.'s paper "Three Dimensionally Stack NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS structure for Beyond 30nm Node", IEEE Int'l Electron Device Meeting, December 11-13, 2006.

In addition, intersection point array technology has also been applied to anti-fuse memory, see the paper "512-Mb PROM with a Three Dimensional Array of Diode/Anti-fuse Memory Cells" by IEEE J. of Solid-state Circuits, vol. 38, no. 11, November 2003. In the design described by Johnson et al., multi-layer word lines and bit lines are used with memory elements at the intersection. The memory element comprises a p+ polysilicon anode connected to a word line, and the n+ polysilicon cathode is connected to the bit line, and the cathode and anode are separated by an antifuse material.

In the process described by Lai, Jung, et al., each memory layer uses multiple key lithography steps. Thus, the number of critical lithography steps required to fabricate this device will be a multiple of the number of memory layers used. Thus, while higher densities can be achieved by using three-dimensional arrays, higher manufacturing costs also limit the scope of use of this technology.

Another technique for using vertical anti-gate memory cell structures in charge trapping memory has also been published in Tanaka et al., "Bit Cost Scaleable Technology with Punch and Plug Process for Ultra High Density Flash Memory", 2007 Symposium on VLSI Technology Digest. Of Technical Papers, pp. 14~15, June 12-14, 2007, described. In the structure described by Tanaka et al., including a multi-gate field-effect transistor structure, which has a vertical channel similar to the anti-gate operation, uses a SONOS type charge trapping memory cell structure to A storage location is created at a gate/vertical channel interface. The memory structure is based on a columnar semiconductor material arranged as a vertical channel to form a multi-gate memory cell having a lower select gate close to the substrate and a higher select gate above it. A plurality of horizontal control gates are formed using a planar electrode layer that intersects the pillars. The planar electrode layer as a horizontal control gate does not require critical lithography, and thus saves cost. However, many critical lithography steps are still required for each vertical memory cell. In addition, the number of control gates in the multilayer structure of this method is still limited, which is determined by factors such as vertical channel conductivity, stylization used, and erase operations.

With this three-dimensional array, memory cells and interconnects can be stacked in a high density manner.

It is therefore desirable to provide a three-dimensional integrated circuit memory structure with low manufacturing cost, including reliable, very small memory components and interconnects and contacts that occupy a small area.

The technique described herein is a three-dimensional memory device having an integrated circuit substrate; a plurality of strips of semiconductor material stacked; a plurality of wires; and a memory element.

The plurality of strips of semiconductor material stack have a ridge shape and include at least two elongated semiconductor materials separated by an insulating layer to form different planar locations in a plurality of planar locations. The plurality of elongated semiconductor material stacks share the same planar position of the plurality of planar locations, and the elongated semiconductor material is connected to the same bit line contact of the plurality of bit line contacts by the stepped structure, such that the step is The steps in the structure are located at the ends of the elongated semiconductor material. In many different embodiments, such a location can save wafer area without connecting bit lines in different layers beyond the ends of the elongated semiconductor material.

The plurality of wires are arranged orthogonal to the plurality of stacks and are conformed to the plurality of stacks such that a three-dimensional array of intersections is established between the surface of the elongated semiconductor material and the plurality of wire intersections.

The memory element is in the intersection region, and the memory cell of the three-dimensional array is accessible via the elongated semiconductor material and the plurality of wires.

The invention also discloses a three-dimensional memory device having an integrated circuit substrate; a plurality of elongated semiconductor material stacks; a plurality of plurality of wires; a memory element; and a plurality of conductive conformal structures.

The plurality of stacks have a ridge shape and include at least two elongated semiconductor materials separated by an insulating layer to form different planar locations in the plurality of planar locations. The elongated semiconductor materials sharing the same planar position in the plurality of planar locations are interconnected.

Many of the plurality of wires include the first, second, and third plurality of wires.

The first plurality of wires are arranged orthogonal to the plurality of stacks and are conformed to the plurality of stacks such that a three-dimensional array of intersections is established between the surface of the elongated semiconductor material and the plurality of wire intersections.

The memory element is in the intersection region, and the memory cell of the three-dimensional array is accessible via the elongated semiconductor material and the plurality of wires.

Each of the electrically conductive conformal structures is over a different stack of the plurality of stacks. In some embodiments, the tandem select line is electrically coupled to the different conductive conformal structures of the plurality of conductive conformal structures via the second plurality of wires and the third plurality of wires.

The second plurality of wires are arranged over the plurality of stacks and are parallel to the elongated semiconductor material. Each of the second plurality of wires is electrically coupled to a different one of the plurality of electrically conductive conical structures.

The third plurality of wires are arranged on the first plurality of wires and parallel to the first plurality of wires, and each of the third plurality of wires is connected to a different one of the second plurality of wires .

In some embodiments, the second plurality of wires and the third plurality of wires are wires in different metal layers that collectively electrically connect the series select signals to different conductive conformal structures.

In addition, a three-dimensional, buried channel, junctionless reverse gate flash structure based on the energy gap engineering polycrystalline germanium-yttria-yttria-yttria-yttria-yttria (BE-SONOS) technique is also described herein.

The objects, features, and embodiments of the present invention will be described in the accompanying drawings.

The following description of the embodiments of the present invention will be described in conjunction with the drawings.

Figure 1 shows a schematic diagram of a 2x2 memory cell portion of a three-dimensional programmable resistive memory array in which the fill material is omitted to clearly represent the stacked and orthogonal wires of the elongated semiconductor material that make up the three dimensional array. In this illustration, only two planes are shown. However, the number of planes can be extended to a very large number. As shown in Fig. 1, the memory array is formed over an integrated circuit substrate having a semiconductor or other structure (not shown) underlying an insulating layer 10. This memory array comprises a stack of a plurality of elongated semiconductor materials 11, 12, 13, 14 separated from one another by insulating materials 21, 22, 23, 24. The stack is ridge shaped and extends along the Y-axis direction in the figure, so the elongated semiconductor materials 11-14 can be configured as bit lines and extend out of the substrate. The elongated semiconductor material 11, 13 can be used as a bit line on the first memory plane, and the elongated semiconductor material 12, 14 can be used as a bit line on the second memory plane. A layer of memory material 15, such as an anti-fuse material, is overlaid on the elongated semiconductor material in this example, and in other examples, at least on the sidewalls of the elongated semiconductor material. A plurality of wires 16, 17 are orthogonal to the stack of elongated semiconductor materials. The plurality of wires 16, 17 have a smooth surface that is stacked with the elongated semiconductor material and filled into the trenches (e.g., 20) defined by the stacks, and stacked and plural between the elongated semiconductor materials 11-14 The intersection of the side surfaces between the strips 16, 17 defines the interface area of the multilayer array. A layer of metal telluride (e.g., tungsten telluride, cobalt telluride, titanium telluride) 18, 19 is formed on the upper surface of the plurality of wires 16, 17.

The memory material layer 15 may comprise an antifuse material such as cerium oxide, cerium oxynitride or other cerium oxide, for example, having a thickness on the order of 1 to 5 nanometers. Other antifuse materials, such as tantalum nitride, can also be utilized. The elongated semiconductor materials 11-14 may be semiconductor materials having a first conductivity type (e.g., p-type). The wires 16, 17 may be semiconductor materials having a second conductivity type (e.g., n-type). For example, the elongated semiconductor materials 11-14 may use p-type polysilicon and the wires 16, 17 may use a heavily doped n+ type polysilicon. The width of the strip of semiconductor material must be sufficient to provide the depletion region required for diode operation. Therefore, the memory cell includes a PN junction formed between the strip polysilicon and the wire rectifier in an array of three-dimensional intersection points, the PN mask having a programmable antifuse layer between the cathode and the anode. In other embodiments, different programmable resistive memory materials can be used, including converting metal oxides, such as tungsten oxide over tungsten or elongated semiconductor materials doped with metal oxide. Such materials can be programmed and erased, and can be used in operational applications where multiple bits are stored in a memory cell.

Figure 2 shows a cross-sectional view along the Z-X plane of the memory cell at the intersection of the conductor 16 and the elongated semiconductor material 14. The active regions 25, 26 form both sides of the elongated semiconductor material 14 and between the wires 16 and the elongated semiconductor material 14. In the natural state, the antifuse memory material layer 15 has a high electrical resistance. After stylization, the anti-fuse memory material collapses, causing one or both of the active regions 25, 26 within the anti-fuse memory material to return to a low resistance state. In the embodiment described herein, each memory cell has two active regions 25, 26 forming the sides of the elongated semiconductor material 14. Figure 3 shows a cross-sectional view along the X-Y plane of the memory cell where the wires 16, 17 meet the elongated semiconductor material 14. The figure shows the current path of the word line defined by the free wire 16 through the antifuse memory material layer 15 to the elongated semiconductor material 14.

The flow of electrons is shown by the solid line in Figure 3, from the n+ wire 16 into the p-type elongated semiconductor material 14, and along the elongated semiconductor material 14 (dashed arrow) to the sense amplifier, at the sense amplifier Measure to indicate the state of the selected memory cell. In an exemplary embodiment, about 1 nm thick yttrium oxide is used as the antifuse material, and a pulse of 5-7 volts and a pulse width of about 1 microsecond are applied using the in-wafer control circuit of FIG. Stylized pulses. The read pulse is applied with a pulse of 1 to 2 volts and a configuration-dependent pulse width using the in-wafer control circuit of FIG. This read pulse can be much shorter than the programmed pulse.

Figure 4 shows two memory cell planes, each with six memory cells. These memory cells are represented by a diode with a layer of antifuse material (represented by dashed lines) between the cathode and the anode. The two memory cell planes are composed of the conductors 16 and 17 as the first word line WLn and the second word line WLn+1 and the first and second sums as the bit lines BLn, BLn+1 and BLn+2, respectively. The intersection of the third strip of semiconductor material stacks 51, 52, 53, 54 and 55, 56 defines the first and second layers of the array. The first plane of the memory cell includes memory cells 30, 31 on the elongated semiconductor material stack 52, memory cells 32, 33 on the elongated semiconductor material stack 54, and memory cells 34 on the elongated semiconductor material stack 56, 35. The second plane of the memory cell includes memory cells 40, 41 on the elongated semiconductor material stack 51, memory cells 42, 43 on the elongated semiconductor material stack 53, and memory cells 44 on the elongated semiconductor material stack 55, 45. As shown in the figure, the wire 60 is used as the word line WLn, which includes vertically extending 60-1, 60-2, 60-3 corresponding to the material in the trench between the stacks in FIG. 1 to connect the wire 60. Coupled with three exemplary strips of semiconductor material in each plane. An array can be implemented with as many layers as described herein to form a very high density memory that approaches or reaches megabits per wafer.

Figure 5 shows a schematic diagram of a 2x2 memory cell portion of a three-dimensional programmable resistive memory array with fill material in the figure to clearly represent the stack and orthogonal conductors of the long strip of semiconductor material that make up the three-dimensional array. . In this illustration, only two layers are shown. However, the number of levels can be extended to very large numbers. As shown in Fig. 5, the memory array is formed over an integrated circuit substrate having a semiconductor or other structure (not shown) underlying an insulating layer 110. This memory array includes a stack 111, 112, 113, 114 of a plurality of elongated semiconductor materials separated from one another by insulating materials 121, 122, 123, 124. The stack is ridge shaped and extends along the Y-axis direction in the figure, so the elongated semiconductor materials 111-114 can be configured as bit lines and extend out of the substrate. The elongated semiconductor material 111, 113 can be used as a bit line on the first memory plane, and the elongated semiconductor material 112, 114 can be used as a bit line on the second memory plane.

The insulating material 121 interposed between the elongated semiconductor materials 111 and 112 in the first stack and the insulating material 123 interposed between the elongated semiconductor materials 113 and 114 in the second stack have an equivalent oxidation of about 40 nm or more. The layer thickness (EOT), wherein the equivalent oxide thickness (EOT) is the thickness of the insulating material multiplied by the thickness of the oxide layer converted by the ratio of the dielectric constant of the tantalum oxide to the insulating layer. The term "about 40 nm" as used herein is the result of an approximately 10% order of magnitude change in the process of a typical such device. The thickness of this insulating layer has an important influence on reducing interference between adjacent memory cells in this structure. In some embodiments, the equivalent oxide thickness (EOT) of the insulating material can be as small as 30 nanometers while still having sufficient isolation between adjacent layers.

A layer of memory material 115, such as a dielectric charge trapping structure, is overlaid over the elongated semiconductor material in this example. A plurality of wires 116, 117 are orthogonal to the stack of elongated semiconductor materials. The plurality of wires 116, 117 have a surface that is stacked with the elongated semiconductor material and filled into the trenches (eg, 120) defined by the stacks, and stacked and plural between the elongated semiconductor materials 111-114 The intersection of the side surfaces between the strips 116, 117 defines the interface area of the multilayer array. A layer of metal telluride (e.g., tungsten telluride, cobalt telluride, titanium telluride) 118, 119 is formed on the upper surface of the plurality of wires 116, 117.

The gold-oxygen half-field effect transistor pattern of the nanowire is also configured in such a way by providing a channel region of the nanowire or nanotube structure over the conductors 111-114, as Paul et al. Impact of a Process Variation on Nanowire and Nanotube Device Performance ", IEEE Transactions on Electron Device, Vol. 54, No. 9, September 11-13, 2007, which is incorporated herein by reference.

Thus, a SONOS-type memory cell configured to be a three-dimensional array of anti-gate flash arrays can be formed. Source, drain and channel are formed in the germanium strip semiconductor material 111-114. The memory material layer 115 includes a tunneling dielectric layer 97 of germanium oxide (O), a charge storage layer 98 of tantalum nitride (N), and oxidation.矽(O) blocks the dielectric layer 99 and the wires 116, 117 of the polysilicon (S).

The elongated semiconductor materials 111-114 may be p-type semiconductor materials and the wires 116, 117 may use the same or different semiconductor materials (e.g., p+ type). For example, the elongated semiconductor materials 111-114 may be p-type polycrystalline germanium or p-type epitaxial single crystal germanium, and the wires 116, 117 may use relatively heavily doped p+ polycrystalline germanium.

Alternatively, the elongated semiconductor materials 111-114 may be n-type semiconductor materials and the wires 116, 117 may use semiconductor materials of the same or different conductivity types (eg, p+ type). This n-type semiconductor material arrangement results in a buried-channel depletion pattern of charge trapping memory cells. For example, the elongated semiconductor materials 111-114 may be n-type polysilicon or n-type epitaxial single crystal germanium, and the wires 116, 117 may use relatively heavily doped p+ polysilicon. The doping concentration of a typical n-type elongated semiconductor material is about 10 ¹⁸ /cm ³ , and the range of embodiments can be used to be between about 10 ¹⁷ /cm ³ and 10 ¹⁹ /cm ³ . The use of n-type strip semiconductor materials is a preferred choice for junctionless embodiments because the conductivity along the anti-gate string and thus the higher read current can be improved.

Thus, this memory cell containing a field effect transistor has a charge storage structure formed in a three dimensional array structure at this intersection. A strip of semiconductor material and wire thickness on the order of about 25 nanometers is used, and the pitch of the ridge-shaped stack is also on the order of about 25 nanometers, and devices having tens of layers (for example, thirty layers) can reach megas in a single wafer (10) ¹² ) The capacity of the bit.

This memory material layer 115 can comprise other charge storage structures. For example, a gap-engineered (BE) SONOS charge storage structure can be used, which includes a dielectric tunneling layer 97 with an inverted U-type valence band at 0V bias between layers. In an embodiment, the multilayer tunneling layer includes a first layer called a tunneling layer, a second layer called a band compensation layer, and a third layer called an isolation layer. In this embodiment, the tunneling layer 97 includes a ruthenium dioxide layer formed on a side surface of the elongated semiconductor material, which may be formed by a method such as in-situ steam generation (ISSG), and optionally Nitriding is carried out by annealing nitric oxide after deposition or by adding nitric oxide during deposition. The thickness of the cerium oxide in the first layer is less than 20 angstroms, and preferably less than 15 angstroms, and in a representative embodiment is 10 -12 angstroms.

In this embodiment, the band compensation layer comprises a tantalum nitride layer on top of the tunnel tunnel layer, and the system uses a technique such as low pressure chemical vapor deposition LPCVD to use dichlorosilane at 680 ° C. DCS) is formed with an ammonia precursor. In other processes, the bandgap compensation layer includes bismuth oxynitride, which is formed using a similar process and a nitrous oxide precursor. The thickness of the tantalum nitride layer in the energy compensation layer is less than 30 angstroms, and preferably 25 angstroms or less.

In this embodiment, the spacer layer comprises a ruthenium dioxide layer on the band compensation layer and is formed by means of LPCVD high temperature oxide HTO deposition. The thickness of the ruthenium dioxide layer in the spacer layer is less than 35 angstroms, and preferably 25 angstroms or less. Such a three-layer tunneling dielectric layer produces a valence band energy level of an "inverted U" shape.

The first valence band energy system allows the electric field to be sufficient to induce tunneling through the thin region between the first portion and the semiconductor body (or strip of semiconductor material) interface, and which is sufficient to enhance the valence band after the first portion Energy level, in order to effectively eliminate the hole tunneling phenomenon in the composite tunneling dielectric layer after the first portion. Such a structure, in addition to establishing the "U-shaped" valence band of the three-layer tunneling dielectric layer, can also achieve electric field-assisted high-speed hole tunneling, which may also exist in the electric field or for other operational purposes (like from In the case where the memory cell reads data or stylizes adjacent memory cells and induces only a small electric field, it effectively prevents charge loss through the composite tunneling dielectric layer structure.

In a representative device, the memory material layer 115 comprises a bandgap engineering (BE) composite tunneling dielectric layer comprising a first layer of cerium oxide having a thickness of less than 2 nanometers and a thickness of a layer of tantalum nitride layer. The thickness of the ceria layer of less than 3 nm and a second layer is less than 4 nm. In one embodiment, the composite tunneling dielectric layer comprises an ultra-thin yttria layer O1 (eg, 15 angstroms or less), an ultra-thin tantalum nitride layer N1 (eg, 30 angstroms or less), and an ultra-thin yttrium oxide layer O2 ( For example, less than or equal to 35 angstroms, and it can increase the valence band energy of about 2.6 electron volts with a compensation of 15 angstroms or less from the interface of the semiconductor body or the strip of semiconductor material. The O2 layer can separate the N1 layer from the charge trapping layer by a second compensation (eg, from about 30 angstroms to 45 angstroms from the interface) by a low energy band energy region (high hole tunneling barrier) and a high conduction band energy level. ). Since the second distance interface is far enough, the electric field sufficient to induce tunneling can increase the valence band energy level after the second portion, so as to effectively eliminate the tunneling barrier. Therefore, the O2 layer does not seriously interfere with the electric field-assisted hole tunneling, and at the same time enhances the ability of the engineered tunneling dielectric structure to resist charge loss at low electric fields.

The charge trapping layer in the memory material layer 115 in this embodiment comprises a tantalum nitride layer having a thickness greater than 50 angstroms, including, for example, tantalum nitride having a thickness of about 70 angstroms, and which is formed using, for example, LPCVD. Other charge trapping materials and structures can also be used in the present invention, including, for example, cerium oxynitride (Si _x O _y N _z ), high cerium-containing nitrides, high cerium oxides, including embedded nanoparticles. Capture layers and more.

The blocking dielectric layer in the memory material layer 115 in this embodiment is yttrium oxide having a thickness greater than 50 angstroms and comprising 90 angstroms in this embodiment, and a wet furnace for wet converting tantalum nitride may be used. Tube oxidation process. In other embodiments, cerium oxide formed by high temperature oxide (HTO) or LPCVD deposition may be used. Other barrier dielectric material such as high dielectric constant materials of alumina can also be used.

In a representative embodiment, the thickness of the cerium oxide in the tunneling layer is 13 angstroms; the thickness of the lanthanum nitride layer of the energy compensation layer is 20 angstroms; and the thickness of the cerium oxide layer of the isolation layer is 25 Å; the thickness of the tantalum nitride layer of the charge trap layer is 70 angstroms; and the barrier dielectric layer may be yttrium oxide having a thickness of 90 angstroms. The gate material of the wires 116, 117 may be p+ polysilicon (having a work function of 5.1 electron volts).

Figure 6 shows a cross-sectional view of the charge trapping memory cell formed at the intersection of the conductor 116 and the elongated semiconductor material 114 along the Z-X plane of the memory cell. The active regions 125, 126 form both sides of the elongated semiconductor material 114 and between the wires 116 and the elongated semiconductor material 114. In the embodiment depicted in FIG. 6, each of the memory cells is a double gate field effect transistor having two active regions 125, 126 forming the sides of the elongated semiconductor material 114.

Figure 7 shows a cross-sectional view of the charge trapping memory cell formed at the intersection of the wire 116 and the elongated semiconductor material 114 along the X-Y plane of the memory cell. The electron flow in the figure is shown by dashed lines along the p-type strip of semiconductor material 114 to the sense amplifier, which can be measured at the sense amplifier to indicate the state of the selected memory cell.

The source/drain regions 128, 129, 130 between the wires 116, 117 as word lines may be "no junction", that is, the source/drain doping type does not need to be associated with word lines. The doping profile of the underlying channel region is different. In this "no junction" embodiment, the charge trapping field effect transistor can have a p-type channel structure. Moreover, in some embodiments, source/drain doping can be formed using auto-aligned implants after defining word lines.

In an alternate embodiment, the elongated semiconductor materials 111-114 may use a lightly doped n-type semiconductor body in a "joint-free" arrangement, resulting in the formation of a buried-channel field effect transistor that can operate in a depletion mode, The charge trapping memory cell has a natural offset to a lower threshold voltage distribution.

Figure 8 shows two memory cell planes, each having nine charge trapping memory cells arranged in a reverse gate configuration, which is a representative example of a cube, which may include many planes and many word lines. The two memory cell planes are composed of wires 160, 161, and 162 as word lines WLn, WLn+1, and WLn+2, which are stacks of first, second, and third elongated semiconductor materials, respectively.

The first plane of the memory cell includes memory cells 70, 71, and 72 in a reverse gate train, and is located on the stack of elongated semiconductor materials, and the memory cells 73, 74, and 75 are in a reverse gate train. And above the stack of elongated semiconductor materials, and the memory cells 76, 77 and 78 are in a reverse gate train and are placed over the stack of elongated semiconductor materials. In this illustration, the second plane of the memory cell corresponds to the bottom plane of the cube, and the memory cells (e.g., 80, 82, and 84) are arranged in the inverse gate train in a manner similar to the first plane.

As shown in the figure, the wire 160 as the word line WLn includes a vertically extending portion corresponding to the material in the trench 120 between the stacks in FIG. 5 to sandwich the wire 160 between the long semiconductor materials and all the planes. The memory cells of the interface region within the trench (e.g., 70, 73, and 76 of the memory cells in the first plane) are coupled.

In this arrangement, the series selection transistors 85, 88 and 89 are connected between the respective AND gate series and the bit line BLn. Similarly, in this arrangement, a similar series-selective transistor connection in the bottom plane is between the respective inverted gate train and bit line BL0. The tandem select lines 106, 107, and 108 connect the gates of the tandem selection transistors between the ridges in each of the planes in a row direction, and in this example provide the serial selection signals SSLn-1, SSLn, and SSLn+1.

In this arrangement, the block selection transistors 90-95 are arranged on the other side of the reverse gate train and are used to column the reverse gates in a selected cube with, for example, ground (shown in Figure 23). The reference source of the example) is coupled. In this example, the ground select line GSL is coupled to the block select transistors 90-95 and can be implemented using conductors 160, 161, and 162. In some embodiments, the tandem selection transistor and the block selection transistor can use the same dielectric stack as the gate oxide layer in the memory cell. In other embodiments, a typical gate oxide layer without memory material can be used instead. In addition, the channel length and width can be adjusted as needed to provide the proper switching of these transistors.

Figure 9 shows a schematic diagram of an alternative structure similar to Figure 5, in which similar reference numerals are used in similar structures and will not be described again. The difference between the ninth and fifth aspects is that the surface 110A of the insulating layer 110 and the side surfaces 113A, 114A of the elongated semiconductor materials 113, 114 are etched into a word line (eg, 160) as a word line. Bare exposed. Thus, the memory material layer 115 can be completely or partially etched between the word lines without affecting operation. However, in some structures it is not necessary to form a dielectric charge trapping structure through the memory material layer 115 as is generally etched as described herein.

Figure 10 shows a cross-sectional view of the memory cell similar to Figure 6 along the Z-X plane. Fig. 10 is exactly the same as Fig. 6, showing the structure in the memory cell of Fig. 9, which is the same as the cross-sectional view of the structure implemented in Fig. 5 in this sectional view. Figure 11 shows a cross-sectional view of the memory cell similar to Figure 7 along the X-Y plane. The difference between the 11th and 7th views is that the memory material in the regions 128a, 129a and 130a along the side surfaces (e.g., 114A) of the elongated semiconductor material 114 is removed. Active regions 125, 126 are formed on both sides of the elongated semiconductor material 114 and between the wires 116 and the elongated semiconductor material 114.

Figures 12 through 16 show a basic process stage flow diagram for implementing a three-dimensional memory array as described herein, using only two patterned mask steps that are critical to the alignment of the array. In Fig. 12, the structure after interleaving the deposition insulating layers 210, 212, 214 and the semiconductor layers 211, 213 is shown. For example, the semiconductor layer can be formed on the array region of the wafer using the fully deposited doped semiconductor. Depending on the embodiment, the semiconductor layer may use polycrystalline germanium or epitaxial single crystal germanium having an n-type or p-type doping. The interlayer insulating layers 210, 212, 214 may be, for example, cerium oxide, other cerium oxide or cerium nitride. These layers can be formed in a number of different ways, including techniques well known in the art, such as low pressure chemical vapor deposition (LPCVD).

Figure 13 shows the results of a first lithographic patterning step for defining a plurality of ridge-like elongated semiconductor material stacks 250, wherein the elongated semiconductor material is comprised of semiconductor layers 211, 213 and is comprised of an insulating layer 210, 212, 214 separated. Ditches with deep and very high aspect ratios can be formed between multilayer stacks using a lithography-based process and applying a carbon-containing hard mask and reactive ion etching.

14A and 14B respectively show a programmable charge memory structure including, for example, an anti-fuse memory cell structure and a programmable charge trap memory structure including, for example, a SONOS type memory cell structure. A section view of the next stage.

Figure 14A shows the results of a comprehensive deposition of a memory material 215 by a programmable resistive memory structure embodiment comprising a single layer anti-fuse memory cell structure as shown in Figure 1. Alternatively, an oxidative process can be performed without the use of a full deposition to form an oxide on the exposed side of the elongated semiconductor material, with the oxide being the memory material.

Figure 14B shows the result of a comprehensive deposition of a memory material 315 comprising a tunneling layer 397, a charge trapping, comprising a programmable resistive memory structure embodiment comprising a multilayer charge trapping structure as shown in Figure 4; Layer 398 and a barrier layer 399. As shown in Figures 14A and 14B, the memory material layers 235, 315 are deposited in a sinuous manner over a ridged strip of elongated semiconductor material (250 in Figure 13).

Figure 15 shows the results of a step of filling a high aspect ratio trench with a conductive material, which may be, for example, an n-type or p-type doped, used as a wire for a word line, to be deposited to form layer 225. Moreover, in embodiments using polysilicon, a layer of germanide 226 is formed over layer 225. As shown in the figure, a polyhedral equal aspect ratio deposition technique such as low pressure chemical vapor deposition (LPCVD) is used in this embodiment to fill the trench between the ridged stacks, even if it is very narrow with a high aspect ratio of 10 Nano-scale ditches are also feasible.

Figure 16 shows the results of a second lithography patterning step for defining a plurality of wires 260 as word lines in the three dimensional memory array. This second lithography patterning step uses a single mask to define the critical dimensions of the etched high aspect ratio trenches in the array without the need to engrave through the ridge-like stack. The polysilicon can be etched using an etching process that is highly selective for polysilicon and tantalum oxide or tantalum nitride. Therefore, instead of the etching process, the same mask as the etching of the semiconductor and the insulating layer can be used, and the process stops at the bottom insulating layer 210.

Figure 17 shows a schematic representation of the manner in which strips of semiconductor material are joined together in a decoding structure and shows a selective implantation step. The illustration of Fig. 17 is rotated 90 degrees on the Z axis such that the Y and Z axes fall on the plane of the paper, unlike Figs. 1 and 16, wherein the X and Z axes fall on the plane of the paper.

In addition, an insulating layer between the ridged stacks of elongated semiconductor material is removed from the figure to show more structural detail.

The multi-layer stack is formed on the insulating layer 410, and includes a plurality of straight lines 425-1, 425-n-1, 425-n ridge-like stacks, and as the word lines WLn, WLn-1, . ..WL1. The plurality of ridge-like stacks include elongated semiconductor materials 412, 413, 414 that are coupled to other elongated semiconductor materials in parallel in the same plane via extensions 412A, 413A, 414A. In other embodiments shown later, the elongated semiconductor material terminates at an extension that forms a stepped structure. The elongated semiconductor material is coupled to the plurality of ridge-like stacked elongated semiconductor materials along the X-axis direction via extensions 412A, 413A, 414A. Moreover, as shown below, these extensions 412A, 413A, 414A extend beyond the edges of the array and are arranged to interface with decoding circuitry within the array to select a plane. These extensions 412A, 413A, 414A can be patterned while or before defining a plurality of ridge-like stacks. In the embodiment shown later, the extension of the stepped structure terminates the elongated semiconductor material and does not need to extend beyond the edges of the array.

The layer of memory material 415 is separated from the strips 425-1 through 425-n by strips of semiconductor material 412-414, which are described in more detail below.

For example, the transistor of transistor 450 is formed between elongated semiconductor materials 412, 413, 414 and conductor 425-1. Among these transistors, a long strip of semiconductor material (e.g., 413) serves as the channel region of the device. The gate structure (e.g., 429) is simultaneously patterned while defining conductors 425-1 through 425-n. A layer of telluride 426 is formed along the upper surface of the wire and over the gate structure 429. The memory material layer 415 can serve as a gate dielectric layer for the transistor. These transistors are coupled as a select gate to the decode circuit to select rows along a ridged stack in the array.

An optional process step includes forming hard masks 401-1 through 401-n over the plurality of wires, and hard masks 402 and 403 over gate structure 429. This hard mask can be formed using relatively thick oxides or other materials that block ion implantation. After the hard mask is formed, ion implantation can be performed to increase the doping concentration in the elongated semiconductor material 412, 413, 414 and extensions 412A, 413A, 414A, and thus reduce the resistance along the current path of the elongated semiconductor material. . By using the control implant energy, the implant can result in a through-strip strip of semiconductor material 412, and each of the elongated semiconductor material in the stack.

Figure 18 is a schematic diagram showing the next stage of manufacturing the memory array shown in Figure 17. The same reference numerals are still used in this figure and will not be described again. The structure shown in Fig. 18 shows the result of removing the hard mask to expose the plurality of wires 425-1 to 425-n and the telluride 426 over the gate structure 429. After an interlevel dielectric layer (not shown) is formed over the array, via holes are formed up to the upper surface of the gate structure 429 and, for example, plugs 458, 459 using tungsten are filled therein. The upper metal lines 460n, 460n+1 as the string selection line SSL are patterned and connected to the row decoding circuit. A three-dimensional decoding circuit is constructed in the manner of a picture, using a word line, a bit line, and a string selection line SSL to access a selected memory cell. See U.S. Patent No. 6,069,940, entitled "Plane Decoding Method and Device for Three Dimensional Memories."

In order to program a selected anti-fuse type memory cell, the word line selected in this embodiment is biased to -7V, and the unselected word line can be set to 0V, and the selected bit line can also be set to 0V, the unselected bit line can be set to 0V, the selected string select line can be set to -3.3V, and the unselected string select line can be set to 0V. In order to read a selected memory cell, the word line selected in this embodiment is biased to -1.5V, the unselected word line can be set to 0V, and the selected bit line can also be set to 0V, which is not selected. The bit line can be set to 0V, the selected string select line can be set to -3.3V, and the unselected string select line can be set to 0V.

Figure 19 provides a top view of this memory cell layout, including tandem select lines and bit lines 470-472 over a ridged stack including strips of semiconductor material 414 and wires 425-n as word lines. These word lines extend to the column decoding circuit.

As shown in the figure, a contact plug (e.g., 458) is coupled to the gate structure to select the elongated semiconductor material 414 to the upper tandem select line (e.g., 460n). One may be referred to as a twisted layout in which the gate structures are shown in an alternately stacked manner such that the alignment boundaries of the patterned contact plug 458 process can be shared along the row direction, thereby reducing the average of the ridged stack layout. spacing. These string select lines extend to the row decode circuit.

Figure 19 also shows a top view of the memory cell layout including a portion of the elongated semiconductor material extension connection (e.g., 414A) to the bit line. As shown in the figure, the extension connection 414A extends beyond the array to the bit line. The via holes are also opened in a staggered manner to expose the elongated semiconductor material extension connections in each of the planes of the array. In this example, junction 481 is formed of a long strip of semiconductor material in a first plane, junction 482 is formed of a long strip of semiconductor material in a second plane, and junction 483 is a strip in the third plane. The composition of semiconductor materials, and so on. Non-critical alignments can be used when forming these contacts with a greater degree of error tolerance as shown in the figure. Bit lines 470, 471, 472 are coupled to contacts 481, 482, 483 and extend parallel to the string select lines to the planar decode circuit and the sense amplifier. In the embodiment shown later, it has a stepped structure that terminates the contacts of the elongated semiconductor and does not need to extend beyond the edges of the array.

Figure 20 shows a cross-sectional view of a memory cell different from the decoder layout of Figure 18 with the Y and Z axes in the plane of the paper. In the embodiment of Fig. 20, an additional patterning step is used to define a tandem select line (e.g., 491) such as a polysilicon, each plane of the array layout being parallel to a wire (e.g., 425-1). The transistor uses a long strip of semiconductor material (e.g., 412) as the channel region. Gate dielectric layer 492 is formed between tandem select line 491 and elongated semiconductor material 412. Telluride 490 can be formed over tandem selection line 491. The tandem select line 491 extends outwardly from the array as described below to the decode circuit. The upper azimuth lines 498 and 499 are connected to the elongated semiconductor material 412, 413, 414 in the respective ridge-like stack via via holes through the structure, and form contact structures 495, 502, 496 and within the via holes. 503.

Figure 21 shows a schematic diagram of the decoder layout in Figure 20, as shown in the figure, a contact (e.g., 502) may be formed between a strip of semiconductor material (e.g., 414) and a bit line (e.g., 498). The contacts are still arranged in a stepped structure such that the alignment boundaries are shared in a plurality of rows.

A tandem select line (e.g., 491) extends outwardly from the array to the upper overall tandem select lines 520, 521, 522. Contact plugs 510, 511, and 512 are formed in the via holes and extend to the tandem select lines in the respective planes of the array. Again, non-critical alignment boundaries (e.g., 513, 514) can be used in forming this structural layout. In this example, the serial select line extends to the planar decode circuit. The bit lines extend to the row decode circuit and the sense amplifier, which are arranged in a page buffer structure to allow for wider, parallel read and write operations. The word line extends to the column decoding circuit.

Figure 22 shows a cross-sectional view of the anti-gate flash array showing the long strip of semiconductor material connected together to a decoding structure and showing the hard mask and a selective implantation step. In Fig. 22, it is rotated so that the Y and Z axes are in the plane of the paper, which is slightly different from Fig. 5, which is the X and Z axes in the plane of the paper.

In addition, the insulating layer between the elongated semiconductor materials in the ridge-like stack is removed from the figure to show more detail.

The multilayer array is formed over an insulating layer 110 comprising a plurality of wires 625-1..., 625-n and a plurality of ridge-like stacked ciss as word lines WLn, WLn-1, ... WL1. The plurality of ridge-like stacks include elongated semiconductor materials 612, 613, 614 that are coupled to other ridge-like stacked elongated semiconductor materials in parallel in the same plane via extensions 612A, 613A, 614A. The extensions 612A, 613A, 614A of the elongated semiconductor materials are arranged along the X-axis direction and coupled to a plurality of ridge-like stacked elongated semiconductor materials. Moreover, as shown below, these extensions 612A, 613A, 614A extend beyond the edges of the array and are arranged to interface with decoding circuitry within the array to select a plane. These extensions 612A, 613A, 614A may be patterned while defining a plurality of ridge-like stacks or prior to the formation of alternately elongated semiconductor materials and insulating layers.

In some embodiments, the elongated semiconductor material extensions 612A, 613A, 614A have an extension of a stepped structure to terminate the elongated semiconductor material 612, 613, 614. These extensions 612A, 613A, 614A can be patterned while defining a plurality of ridge-like stacks.

A layer of memory material 615 separates conductors 625-1 through 625-n from strips of semiconductor material 612-614 as previously described.

For example, the transistor of transistor 650 is formed between elongated semiconductor material extensions 612A, 613A, 614 and conductor 625-1. Further, a transistor such as transistor 651 forms the opposite side of the elongated semiconductor material to control the connection of the segments of the array to a common source line (not shown). In these transistors 650, 651, a long strip of semiconductor material (e.g., 612) acts as a channel region for the device. The gate structures (e.g., 629, 649) are simultaneously patterned while defining conductors 625-1 through 625-n. This ground selection line GSL 649 can be arranged along the column direction and through a plurality of ridge-like stacked strips of semiconductor material. A layer of germanide 626 is formed over the upper surface of the wire and over the gate structures 629, 649. The memory material layer 615 can serve as a gate dielectric layer for the transistor. These transistors 650, 651 are coupled as a select gate to a decode circuit to select segments and rows along a ridge-like stack in the array.

An optional process step includes forming hard masks 601-1 through 601-n over a plurality of wires, hard mask 648 over ground select line GSL 649, and hard masks 602 and 603 at gate structure 629. on. This hard mask can be formed using relatively thick oxides or other materials that block ion implantation. After the hard mask is formed, n-type or p-type ion implantation 600 can be performed depending on the application being performed to increase the doping concentration in the elongated semiconductor materials 612-614 and extensions 612A-614A, and thus reduce the strip along the strip The resistance on the current path of the semiconductor material. In addition, if necessary, the doped impurities are opposite to the conductivity type of the bulk strip semiconductor material (eg, when the bulk strip semiconductor material is p-type, n-type ion implantation is performed) to follow the strip semiconductor The material forms a doped source/drain junction. By using the control implant energy, the implant can result in a through-strip strip of semiconductor material 612, and each of the elongated strips of semiconductor material in the stack.

In order to program a selected reverse gate flash SONOS type memory cell, the word line selected in this embodiment is biased to +20V, and the unselected word line can be set to +10V, and the selected bit line is selected. It can also be set to 0V, the unselected bit line can be set to 0V, the selected string selection line can be set to 3.3V, and the unselected string selection line and the ground selection line GSL can be set to 0V. In order to read a selected memory cell, the word line selected in this embodiment is biased to the read reference voltage, the unselected word line can be set to 6V, and the selected bit line can also be set to 1V, The selected bit line can be set to 0V, the selected string selection line can be set to 3.3V, and the unselected string selection line can be set to 0V.

Fig. 23 is a view showing the next stage of manufacturing the memory array shown in Fig. 22. The same reference numerals are still used in this figure and will not be described again. The structure shown in Fig. 23 shows the result of removing the hard mask to expose the plurality of wires 625-1 to 625-n and the germane 626 over the gate structures 629 and 649. After an interlevel dielectric layer (not shown) is formed over the array, via holes are formed up to the upper surface of the gate structure 629 and, for example, plugs 665, 666 using tungsten are filled therein. Further, a common metal source line 670 is formed and connected to the end of the elongated semiconductor material adjacent to the selection transistor 651. The upper metal lines 665, 666 are patterned to connect to the row decode circuit via the connection plugs 665, 666 and the serial select gates and connections.

Figure 24 provides a top view of this memory cell layout, including a tandem select line (e.g., 661) and bit lines 671-673, which are ridged including a strip of semiconductor material 614 and a conductor 625-n as a word line. Above the stack. These word lines extend to the column decoding circuit. In addition, the ground select line GSL 649 located below the string select line is also shown and extends parallel to the word line to the sector decoder. Also shown is a common source line 670 located below the string selection line, and is also parallel to the word line.

As shown in the figure, a contact plug (e.g., 665) is coupled to the gate structure to select the elongated semiconductor material 614 to the upper tandem select line (e.g., 661). A twisted layout can be used in which the gate structures are shown in an alternately stacked manner such that the alignment boundaries of the patterned contact plug 665 process (e.g., 665A) can be shared along the row direction, thereby reducing the ridge shape. The average spacing of the stacked layouts. These string select lines extend to the row decode circuit.

Figure 24 also shows a top view of the memory cell layout including a portion of the elongated semiconductor material extension connection (e.g., 614A) to the bit line. As shown in the figure, the extension connection 614A extends beyond the array to the bit line. The via holes are also opened in a staggered manner to expose the elongated semiconductor material extension connections in each of the planes of the array. In this example, the contact 681 is formed of a long strip of semiconductor material that reaches the first plane, the junction 682 is formed of a long strip of semiconductor material that reaches the second plane, and the junction 683 is reached by the third plane. The composition of the long strip of semiconductor material, and so on. Non-critical alignments can be used when forming these contacts with a greater degree of error tolerance as shown at 680 in the figure. Bit lines 670, 671, 672 are coupled to contacts 681, 682, 683 and extend parallel to the string select lines to the planar decode circuit and the sense amplifier. In the embodiment shown later, it has a stepped structure that terminates the contacts of the elongated semiconductor and does not need to extend beyond the edges of the array.

Fig. 25 is a cross-sectional view showing the Y and Z axes in the plane of the paper, showing the structure in which the extension joints 612A to 614A are connected to the contact plugs 681, 682, and 683, respectively. The upper azimuth lines 670~672 are connected to the connecting plug. The alignment boundaries 680a, 680b of the contact plugs 681-683 show that the patterning of this step is not critical and does not affect the density of the array. The other reference numerals shown in the figures are the same as those previously used, and these structures will not be described again.

Figure 26 is a cross-sectional view showing an embodiment of the anti-gate flash array, in which the Y and Z axes are in the plane of the paper, which is slightly different from Fig. 23. In the embodiment of Figure 26, an additional patterning step is used to define a tandem select line (e.g., 691) and a ground tandem select line (e.g., 649) using polysilicon, in which each plane of the array is associated with a wire (e.g., 625-1) Parallel. The transistors 700 and 702 are formed as a result of the use of lines 691 and 649 using elongated semiconductor materials as channel regions. A gate dielectric layer 692 is applied between the string select line 691 and the elongated semiconductor material 612 and between the ground select line 649 and the elongated semiconductor material 612. A layer of germanide 690 is formed over series select line 691 and ground select line 649. The string select line 691 extends outward from the array as described below to interface with the decode circuitry. The upper orientation element lines 698, the via holes that open through the structure are connected to the elongated semiconductor material 612, 613, 614 in respective ridge-like stacks, and the contact structures 695, 702, 693, 703 are formed within the via holes.

Figure 27 shows a schematic diagram of the decoder layout in Figure 26, as shown in the figure, a junction (e.g., 705) may be formed between a strip of semiconductor material (e.g., 614) and a bit line (e.g., 698). The contacts are still arranged in a stepped structure such that the alignment boundaries are shared in a plurality of rows.

A tandem select line (e.g., 649) extends outwardly from the array to the upper overall tandem select lines 720, 721, 722. Contact plugs 710, 711, and 712 are formed in the via holes and extend to the tandem select lines in the respective planes of the array to the upper overall tandem select lines 720, 721, 722. Again, non-critical alignment boundaries (e.g., 713, 714) can be used in forming this structural layout. In this example, the serial select line extends to the planar decode circuit. In certain embodiments shown later, the elongated semiconductor material extends with an extension of the stepped structure to terminate the elongated semiconductor material 612 and does not need to extend beyond the edges of the array. The bit lines extend to the row decode circuit and the sense amplifier, which are arranged in a page buffer structure to allow for wider, parallel read and write operations. The word line extends to the column decoding circuit.

In addition, the ground selection line GSL649 below the bit line is also shown and extends parallel to the word line to the sector decoder. Also shown is a common source line 670 below the bit line and also parallel to the word line (e.g., 625n) to the common source line 725 above the contact plug 680 level above the array.

Figure 28 is a simplified schematic diagram of an integrated circuit in accordance with an embodiment of the present invention. The integrated circuit 875 includes the use of a three-dimensional programmable resistive read only memory (RRAM) array 860 as described herein over a semiconductor substrate. A column of decoders 861 is coupled to and electrically coupled to a plurality of word lines 862 arranged along the direction of the column of memory array 860. Row decoder 863 is in electrical communication with a plurality of bit lines 864 (or string select lines as previously described) arranged along the row direction of memory array 860 to read and program data from memory cells of array 860. . A planar decoder 858 is coupled to the previously described string select line 859 on the array 860 plane. The address is provided by bus 865 to row decoder 863, column decoder 861 and plane decoder 858. The sense amplifier and data input structure in block 866 is coupled to row decoder 863 via data bus 867. The data is provided to the data input line 871 by the input/output ports on the integrated circuit 875, or to other data sources of the integrated circuit 875, to the data input structure in block 866. Other circuits 874 are included within integrated circuit 875, such as a general purpose processor or special purpose application circuit, or a combination of modules to provide system single chip functionality supported by a programmable resistive memory cell array. The data is provided by sense amplifiers in block 866, via data output line 872, to integrated circuit 875, or to other data terminals internal/external to integrated circuit 875.

The controller used in this embodiment uses a bias adjustment state mechanism 869 and controls the application of the bias adjustment supply voltage 868, such as read and program voltage. The controller can be utilized with special purpose logic circuitry as is well known to those skilled in the art. In an alternate embodiment, the controller includes a general purpose processor that can be used in the same integrated circuit to execute a computer program to control the operation of the device. In yet another embodiment, the controller is a combination of special purpose logic circuitry and a general purpose processor.

Figure 29 is a simplified schematic diagram of an integrated circuit in accordance with an embodiment of the present invention. The integrated circuit 975 includes the use of a three-dimensional three-dimensional inverse gate flash memory array array 960 as described herein over a semiconductor substrate. A column of decoders 961 is coupled to and electrically coupled to a plurality of word lines 962 arranged along the direction of the column of memory arrays 960. Row decoder 963 is in electrical communication with a plurality of bit lines 964 (or string select lines as previously described) arranged along the row direction of memory array 960 to read and program data from memory cells of array 960. . A planar decoder 958 is coupled to the previously described string select line 959 on the array 960 plane. The address is provided by bus 965 to row decoder 963, column decoder 961 and plane decoder 958. The sense amplifier and data input structure in block 966 is coupled to row decoder 963 via data bus 967. The data is supplied to the data input line 971 by the input/output port on the integrated circuit 975, or is input to the data input structure in block 966 by other internal/external data sources of the integrated circuit 975. In this exemplary embodiment, other circuits 974 are included in the integrated circuit 975, such as a general purpose processor or a special purpose application circuit, or a combination of modules to provide support by the anti-gate flash memory array. System single chip function. The data is provided by the sense amplifier in block 966, via the data output line 972, to the integrated circuit 975, or to other data terminals internal/external to the integrated circuit 975.

The controller used in this embodiment uses a bias adjustment state mechanism 969 and controls the application of the bias adjustment supply voltage 968, such as reading, programming, erasing, erasing verification, and stylized verification. Voltage. The controller can be utilized with special purpose logic circuitry as is well known to those skilled in the art. In an alternate embodiment, the controller includes a general purpose processor that can be used in the same integrated circuit to execute a computer program to control the operation of the device. In yet another embodiment, the controller is a combination of special purpose logic circuitry and a general purpose processor.

Figure 30 is a cross-sectional view of a tunneling electron microscope of a portion of a 8-layer vertical channel thin film transistor energy gap engineering polycrystalline germanium-yttria-yttria-yttria-yttria-yttria (BE-SONOS) charge trapping gate device. It is manufactured, tested and arranged for decoding in the manner of Figures 8 and 23. This device was formed using a half pitch of 75 nm. The channel is an approximately 180 nm thick n-type polysilicon. No joints were implanted to form a jointless structure. The insulating material used to isolate the channels between the semiconductor strips is in the Z-axis direction and is a tantalum oxide having a thickness of about 40 nm. The gate provided is extremely P+ polysilicon. This serial selection and ground selection device has a longer channel length than the memory cell. The test device has 32 word lines, no junctions, and gate series. Since the trench etch used to form the structure shown has an inclined shape, a wide ridge line is formed at the bottom of the trench, and the insulating material between the thin lines is etched more from the polysilicon, so the width of the lower thin line in Fig. 30 It is wider than the width of the upper thin line.

This device can be programmed using positive and negative Le-Nordheim electron tunneling. This embodiment uses an incremental step-up pulse stylization (ISSP) operation of self-pressurization. The stylized bias of the selected memory cell can be understood in conjunction with Figure 8, and the interference of adjacent memory cells will also be discussed. To program memory cells A (74) at BLn, SSLn, and WLn, a stylized potential is applied to WLn, SSLn is set to Vcc (about 3.3V), and bit line BLn is set to about 0V. GSL is also set to about 0V. WLn-1 and WLn+1 (and other word lines in this series) are set to the turn-on voltage. SSLn-1 and SSLn+1 (and other serial select lines in this cube) are set to approximately 0V. Other bit lines, such as bit line BL ₀ , are set to be about 3.3V to suppress interference. GSL is also set to about 0V. An incremental step-pulse stylization (ISSP) program involves the application of incremental step-programmed pulses to word lines ranging from 14V to 20V. A turn-on voltage of about 10 V is applied to the other word lines.

The following describes the interference of this stylized bias to adjacent memory cells, respectively, for BLn, SSLn+1 (adjacent ridges in the same layer of the same word line) and memory cell B (77) of WLn, for BL0 , SSLn (the same ridge in different layers of the same word line) and memory cell C of WLn, for BL0, SSLn+1 (adjacent ridges in different layers of the same word line) and memory cell D of WLn, Memory cell E (73) for BLn, SSLn, and WLn-1 (the same ridge in the same layer of adjacent word lines).

The gate of memory cell B receives the stylized potential through WLn, and its channel is floating, which causes self-boosting. Therefore, stylized interference is avoided.

The gate of memory cell C receives the stylized potential through WLn, and its channel is floating, which causes self-boosting. Therefore, stylized interference is avoided. However, for adjacent planes, the interference can still occur due to the fringing electric field induced by the voltage change in the memory cell A. Therefore, the separation between the planes should be sufficient to suppress the interference in the Z direction. The simulation results suggest that the thickness of the insulating material between the planes should be set to at least 30 nm, and preferably 40 nm or more to suppress interference caused by interference in the Z direction.

The gate of memory cell D receives the stylized potential through WLn, while its channel is floating, which causes self-boosting. Therefore, stylized interference is avoided.

The gate of the memory cell E receives the turn-on voltage through WLn-1, and its channel is coupled to the BLn of about 0V via the anti-gate string. This stylized turn-on voltage should be on the order of 10V to suppress this memory cell interference.

This device can be erased using a negative gate and a voltage negative-Nordheim tunnel. Applying an erase voltage ranging from -16 to -12V, the selected word line can be set to receive the erase voltage, and the other word lines in the series receive the turn-on voltage and the selected bit line can be set to about 0V.

The inverse of the vertical gate of the three-dimensional buried channel described herein and the gate array are suitable for miniaturization to a small size because the channel width is mostly related to the thickness of the elongated semiconductor material rather than its width. The spacing is thus limited by the thickness of the trench required to deposit the charge trapping structure and fill the word line, and the minimum feature size achievable by the stack width. Furthermore, this structure can be fabricated with fewer mask steps, thus greatly reducing the cost per memory cell.

Figure 31 shows a layout diagram that supports three-dimensional vertical gate reversal and gate flash or a very efficient array decoding and memory architecture design for other techniques. As shown in Fig. 31, the layout diagram omits (compared with Fig. 24) bit lines which are above the ridge-like stack and the tandem selection metal lines. This character line extends to the column decoding circuit. In addition, the ground select line 649 is below the tandem select line and extends parallel to the word line to a sector decoder. A metal common source line 670 extends below the string select line and is parallel to the word line.

As shown, a contact plug (e.g., 665) is coupled to the gate structure to select the elongated semiconductor material 614 to an upper series of select line segments that are parallel to the ridge-like stack. A type of twisted layout is used in which the gate structure is arranged in a stepped manner as shown in the figure such that the patterned conductive plugs 665 are aligned in a plurality of columns to reduce the ridge stack in this layout. Average spacing. This series of select line segments extends along the ridged stack until the end of the stagger. These end points may, for example, be staggered such that the bottommost tandem select line segment reaches the upper region of the rightmost character line and the next tandem select line segment reaches above the rightmost second strip of character lines. The area, the next string selection line segment reaches the upper area of the third rightmost character line, and so on. The contacts are placed at the end of the staggered line segment interleaving to be connected to the upper horizontal tandem select line, which extends parallel to the word line to the tandem select decoding circuit, which can be placed with the word line The layout of the decoding circuit is in the column decoding area. The spacing of the string selection lines is greater than the spacing of the word lines. In this example layout, each column of cubes can have 32 word lines (plus a ground selection line) and 16 8-layer deep ridges. Stacking. The result is the use of 16 horizontal string select lines and 32 word line lines in the column decode area. Eight bit lines are coupled to eight of the 16 ridge-shaped stacks. Such a word line is decoded to select a column, the string selection line is decoded to select a row, and the bit line is decoded to select a plane. This provides a cubic structure with 32x16x8 memory cells. Of course, other combinations of word lines, string selection lines, and bit lines can also be used. It is also possible to add a dummy word line, for example two dummy word lines in each string.

Figure 31 shows a block labeled "Bitline Step Contact Structure" which is implemented as described below to provide planar decoding and to couple the selected plane to the sense amplifier. The via holes are opened in a staggered or stepped manner to expose the elongated semiconductor material in each of the array planes. Again, non-critical alignment boundaries with relatively large tolerance values can be used in forming this contact structure layout.

The array layout shown here can be repeated using mirror symmetry, with adjacent cubes sharing contact at the end of the stepped bit line, and adjacent cubes sharing a common source line at the ground select line end.

Figure 32 is a cross-sectional view of an alternative embodiment of a memory array having a stepped structure termination bit line (compared to Figure 23). The same reference numerals are still used in this figure and will not be described again. The structure shown in Fig. 23 shows the result of removing the hard mask to expose the plurality of wires 625-1 to 625-n and the germane 626 over the gate structures 629 and 649. After an interlevel dielectric layer (not shown) is formed over the array, via holes are formed up to the upper surface of the gate structure 629 and, for example, plugs 665, 666 using tungsten are filled therein. Further, a common metal source line 670 is formed and connected to the end of the elongated semiconductor material adjacent to the selection transistor 651.

The upper metal lines 665, 666 are patterned to connect to the row decode circuit via the connection plugs 665, 666 and the serial select gates and connections. In this figure, the twisted gate layout is not shown, but it is still best to use it.

The elongated semiconductor material extensions 612A, 613A, 614A form a stepped structure that terminates the elongated semiconductor materials 612, 613, 614. The extensions 612A, 613A, 614A of these elongated semiconductor materials can be patterned along with the definition of a plurality of ridge-like stacks.

Figure 33 shows a cross-sectional view of a memory array having a stepped structure termination bit line and having a staggered contact plug and a string select line connection (compared to Figure 32).

The upper metal lines 661 and 662 are patterned to select and connect the line and via the connection plugs 665, 666 and are coupled to the row decode circuit. In this figure, the twist gate layout is shown. But it's better still to use. The gate structures are arranged in a staggered manner as shown in the figures such that they can be shared along a plurality of column contacts during formation of the conductive contact plug patterning process, reducing the average spacing in this ridge-like stack layout.

Figure 34 is a schematic diagram of the next stage of fabricating the memory array shown in Figure 33, in which the bit line contacts are connected to different steps of the stepped structure (as compared to Figure 33).

As shown in the figure, the tandem select line segments are parallel to the ridge-like stack, which arrive at the contact plugs in a staggered manner to connect with the upper tandem select line, as described in FIG. 31, the tandem select line It is perpendicular to this ridge-like stack and parallel to the word line. The bit line is also shown in the figure, which is the higher metal layer above the tandem selection line.

Figure 35 is a circuit diagram showing the implementation of the anti-gate flash device described in Figures 31 and 32. Shows detailed layout and design plans for different technology nodes. This solution is very efficient and cost-effective for 3D anti-gate flash devices over 128GB and megabits.

Figure 36 shows a plan view of one possible two array embodiment.

In one embodiment there is a density of 8 GB (equal to 64 Gbits or 64 Gb): the details are as follows: In both the word line and the DIFF (serial selection line device), the half-pitch of the design criteria is 65 nm. A three-dimensional VGNAND with an 8-layer memory layer.

The bit line (third metal layer) pitch is equal to 2 x DIFF pitch = 260 nm.

The tandem selection line (second metal layer) pitch is equal to 2 x WL pitch = 260 nm.

Density is 8Gb (8-layer memory layer, multi-level memory cell (2-bit/memory cell))

The page size is 4kB (2-bit/memory cell), the block size is 2MB=32*16 pages, and the plane size is 4GB (2000 blocks)

Grain size ~150 mm 2 (array = 107 mm 2 )

In another embodiment, there is a 64GB density (equal to 512G bits or 512Gb): the details are as follows: in both the word line and the DIFF (serial selection line device), the half-pitch of the design criteria is 32 nm. A three-dimensional VGNAND with a 16-layer memory layer.

The bit line (third metal layer) pitch is equal to 2 x DIFF pitch = 128 nm.

The tandem selection line (second metal layer) pitch is equal to 2 x WL pitch = 128 nm.

Density is 512Gb (8-layer memory layer, multi-level memory cell (2-bit/memory cell))

The page size is 8kB (2-bit/memory cell), the block size is 16MB=64*32 pages, and the plane size is 32GB (2000 blocks)

Grain size ~140 mm 2 (array = 97 mm 2 )

Because of the extra string selection line, this XDEC (column decoding) area is 1.5 times that of the conventional multi-level memory cell. XDEC (column decoding) can be located on one side or both sides.

Other micro-shrink conditions are listed below, which have a 2-bit/memory cell operation: with 8 memory layers, 128 Gb with 45 nm 4F ² ; 256 Gb with 32 nm 4F ² ; 256 Gb with 25 nm 5.1 F ² ; (X is 32 nm half pitch, Y is 25 nm half pitch)

Has 16 layers of memory, 512Gb with 32nm 4F ² or 25nm 5.1F ² ; 32 layers of memory, 1Tb with 42nm 4F ² or 25nm 5.1F ² ; In an embodiment, it can be designed as a multi-plane memory for other different technology nodes.

The number of memory layers is not limited to 8, 16, or 32. Other embodiments may have other numbers, such as other 2x or a half node such as 12, which is a half node between 8 and 16.

The preferred embodiments and examples of the present invention are disclosed in detail above, but it should be understood that the above examples are merely exemplary and are not intended to limit the scope of the patent. For those skilled in the art, the related art can be modified and combined easily according to the scope of the following patent application.

10, 110. . . Insulation

11~14, 111~114. . . Long strip of semiconductor material

15, 115. . . Memory material

16, 17, 116, 117. . . wire

18, 19, 118, 119. . . Metal telluride

20, 120. . . ditch

21~24, 121~124. . . Insulation Materials

25, 26, 125, 126. . . Active area

30~35, 40~45, 70~79, 80, 82, 84. . . Memory cell

51~56. . . Long strip of semiconductor material stack

60 (60-1, 60-2, 60-3), 61, 160~162. . . wire

90~95. . . Block selection transistor

97, 397. . . Tunneling dielectric layer

98, 398. . . Charge storage layer

99, 399. . . Blocking dielectric layer

85, 88, 89. . . Tandem selection transistor

106, 107, 108. . . Serial selection line

128, 129, 130. . . Source/bungee area

210, 212, 214. . . Insulation

211, 213. . . semiconductor

215. . . Memory material layer

250. . . Ridge stack

315. . . Charge trapping layer

225, 260. . . wire

226, 426, 490, 626. . . Metal telluride

400. . . Ion implantation

401-1~401-n. . . Hard mask

402, 403. . . Hard mask

410. . . Insulation

412~414. . . Long strip of semiconductor material

412A~414A. . . Long strip of semiconductor material extension

415. . . Memory material

425-1~425-n, 460-1~460-n. . . wire

429. . . Gate structure

450, 500. . . Transistor

458, 459, 510, 511, 512. . . Contact embolization

470, 471, 472. . . Bit line

480. . . Contact boundary

481~483. . . contact

491. . . Serial selection line

492. . . Gate dielectric layer

498, 499. . . Bit line

495, 496, 502, 503. . . Contact structure

520, 521, 522. . . Overall serial selection line

513, 514. . . Alignment boundary

600. . . Ion implantation

601-1~601-n. . . Hard mask

602, 603, 648. . . Hard mask

610. . . Insulation

612~614. . . Long strip of semiconductor material

612A~614A. . . Long strip of semiconductor material extension

615. . . Memory material

625-1~625-n, 460-1~460-n. . . wire

629, 649. . . Gate structure

650, 651. . . Transistor

661, 662. . . Serial selection line

671, 672, 673. . . Bit line

665, 666, 680. . . Contact structure

665A. . . Contact boundary

670, 725. . . Common source line

680a, 680b, 713, 714. . . Alignment boundary

681~683, 710~712. . . Contact embolization

691. . . Serial selection line

692. . . Gate dielectric layer

698, 699. . . Bit line

695, 696, 702, 703, 705. . . Contact structure

720, 721, 722. . . Overall serial selection line

875, 975. . . Integrated circuit

860. . . Automatic alignment of three-dimensional programmable resistance read-only memory array

960. . . Automatic alignment of three-dimensional anti-gate flash memory array

858, 958. . . Planar decoder

859, 959. . . Serial selection line

861, 961. . . Column decoder

862, 962. . . Word line

863, 963. . . Row decoder

864, 964. . . Bit line

865, 965, 867, 967. . . Busbar

866, 966. . . Sense amplifier / data input structure

874, 974. . . Other circuit

869, 969. . . State agency

868, 968. . . Bias adjustment supply voltage

871, 971. . . Data input line

872, 972. . . Data output line

Figure 1 shows a schematic diagram of a memory cell portion of a three-dimensional programmable resistive memory array comprising a plurality of strips of semiconductor material plane parallel to the Y-axis and arranged in a plurality of ridge-like stacks, a memory layer over the elongated semiconductor material The sides, and the plurality of wires having the bottom surface of the plurality of ridge-shaped stacked compliant bottoms.

Fig. 2 is a cross-sectional view showing the memory cell structure of Fig. 1 along the Z-X plane.

Fig. 3 is a cross-sectional view showing the memory cell structure of Fig. 1 along the Y-X plane.

Fig. 4 is a view showing the structure of the antifuse having the structure of Fig. 1 as a basic memory.

Figure 5 is a schematic diagram showing a memory cell portion of a three-dimensional inverse gate flash memory structure including a plurality of strips of semiconductor material plane parallel to the Y-axis and arranged in a plurality of ridge-like stacks, a charge trapping memory layer being long The sides of the strip of semiconductor material, and the plurality of strips having the bottom surface of the plurality of ridge-shaped stacked compliant bottoms.

Fig. 6 is a cross-sectional view showing the memory cell structure of Fig. 5 along the Z-X plane.

Fig. 7 is a cross-sectional view showing the memory cell structure of Fig. 5 along the Y-X plane.

Fig. 8 is a view showing the reverse gate flash memory having the structure of Fig. 5.

Figure 9 shows a schematic diagram of an alternative embodiment of a three-dimensional inverse gate flash memory structure similar to that of Figure 5, in which the layer of memory material is removed from between the wires.

Fig. 10 is a cross-sectional view showing the memory cell structure of Fig. 9 along the Z-X plane.

Fig. 11 is a cross-sectional view showing the memory cell structure of Fig. 9 along the Y-X plane.

Fig. 12 is a schematic cross-sectional view showing the first stage of the process for fabricating the memory device of Figs. 1, 5, and 9.

Figure 13 shows a schematic cross-sectional view showing the second stage of the process for fabricating the memory device of Figures 1, 5, and 9.

Fig. 14A shows a schematic cross-sectional view showing the third stage of the process of manufacturing the memory device as shown in Fig. 1.

Fig. 14B shows a schematic cross-sectional view showing the third stage of the process of manufacturing the memory device as shown in Fig. 5.

Fig. 15 is a cross-sectional view showing the third stage of the process of manufacturing the memory device as shown in Figs. 1, 5, and 9.

Fig. 16 is a schematic cross-sectional view showing the fourth stage of the process of manufacturing the memory device as shown in Figs. 1, 5, and 9.

Figure 17 is a schematic view of a tandem selection structure rotated 90 degrees on the Z-axis, and also shows a cross-sectional view of the fifth stage of the process for fabricating the memory device of Figure 1, including a hard mask and optional Planting steps.

Figure 18 shows a schematic diagram of the anti-fuse as a serial selection structure of the underlying memory.

Figure 19 provides a top view similar to the device layout in Figure 18, showing the interconnections between the planar decoding structures.

Figure 20 shows a schematic diagram of the anti-fuse as an alternative serial selection structure for the underlying memory.

Figure 21 provides a top view similar to the layout of the device in Figure 20.

Figure 22 is a schematic view showing a tandem selection structure for rotating the Z-axis of Figure 5 by 90 degrees, and also showing a cross-sectional view of the fifth stage of the process for manufacturing the memory device of Figure 5, including a hard Curtain and optional planting steps.

Figure 23 is a diagram showing the reverse selection of the gate flash as the serial selection structure of the underlying memory, including a common source line.

Figure 24 provides a top view similar to the layout of the device in Figure 23, showing the interconnections between the planar decoding structures.

Fig. 25 is a view similar to the plane decoding structure in Fig. 24, showing its bit line structure.

Figure 26 shows a schematic diagram of the alternative tandem selection structure of the underlying memory flash.

Figure 27 provides a top view similar to the layout of the device in Figure 26.

Figure 28 is a simplified schematic diagram of an integrated circuit in accordance with an embodiment of the present invention, wherein the integrated circuit includes a three-dimensional programmable resistive read-only memory array having rows, columns, and decoding circuits.

Figure 29 is a simplified schematic diagram of an integrated circuit in accordance with another embodiment of the present invention, wherein the integrated circuit includes a three-dimensional inverse NAND flash memory array having rows, columns and decoding circuits.

Figure 30 is a tunneling electron micrograph of a portion of a three-dimensional inverse gate flash memory array.

Figure 31 shows a top view of the serial selection line layout.

Figure 32 shows a schematic diagram of an alternate embodiment memory array having a staircase structure termination bit line plane.

Figure 33 shows a schematic diagram of another alternate embodiment memory array having a stepped structure termination bit line plane and a step contact plug of the pole connection string select line.

Figure 34 is a cross-sectional view showing the next stage of the process of fabricating the memory device of Figure 33, wherein the bit line contacts are connected to different step positions in the step structure.

Figure 35 is a circuit diagram showing the implementation of the anti-gate flash device described in Figure 34.

Figure 36 shows a plan view of one possible two array embodiment.

10. . . Insulation

11~14. . . Long strip of semiconductor material

15. . . Memory material

16, 17. . . wire

18, 19. . . Metal telluride

20. . . ditch

21~24. . . Insulation Materials

Claims (22)

A memory device comprising: an integrated circuit substrate; a plurality of elongated semiconductor material stacks extending out of the integrated circuit substrate, the plurality of stacks comprising at least two elongated semiconductor materials separated by an insulating layer into a plurality of planar locations The plurality of planar locations, the plurality of semiconductor materials sharing the same planar position of the plurality of planar locations are connected by a stepped structure to one of the plurality of bitline contacts, such that the stepped a step in the structure is located at an end of the plurality of strips of semiconductor material; a plurality of wires are arranged orthogonal to the plurality of stacks and conform to the plurality of stacks, such that the surface of the plurality of strips of semiconductor material And intersecting the plurality of wire intersections to establish a three-dimensional array of intersection regions; and the memory component is in the intersection region, and the memory cells of the three-dimensional array are accessible via the plurality of semiconductor materials and the plurality of wires. The memory device of claim 1, further comprising: a decoding circuit coupled to the plurality of semiconductor materials and the plurality of wires in the plurality of stacks to access the memory cell. The memory device of claim 1, wherein the memory element comprises an anti-fuse. The memory device of claim 1, wherein the memory element comprises a charge storage structure. The memory device of claim 1, wherein the memory cell comprises a buried channel charge storage transistor. The memory device of claim 1, wherein the plurality of semiconductor materials in the plurality of stacks comprise doped semiconductors. The memory device of claim 1, wherein the plurality of wires comprise a doped semiconductor. The memory device of claim 1, wherein the memory element comprises a portion of a common layer of memory material between the plurality of stacks and the plurality of wires. The memory device of claim 1, comprising a tunneling layer, a charge trapping layer and a barrier layer between the plurality of stacks and the plurality of wires, wherein the tunneling layer, the charge trapping layer and the blocking layer The combination of layers constitutes the memory element in the intersection area. The memory device of claim 1, further comprising a plurality of bit lines arranged on the plurality of stacks and parallel to the plurality of strips of semiconductor material, wherein different bit lines of the plurality of bit lines are via The plurality of bit line contacts and the stepped structure are electrically connected to different planar positions in the plurality of stacks. A memory device comprising: an integrated circuit substrate; a plurality of elongated semiconductor material stacks extending out of the integrated circuit substrate, the plurality of stacks comprising at least two elongated semiconductor materials separated by an insulating layer into a plurality of planar locations The different planar positions, the plurality of semiconductor materials sharing the same planar position of the plurality of planar positions are connected by a stepped structure to one of the plurality of bit line contacts, such that the step is a step in the structure is located at an end of the plurality of strips of semiconductor material; the first plurality of wires are arranged orthogonal to the plurality of stacks, and conform to the plurality of stacks, such that the plurality of strips of semiconductor material The surface is established with the intersection of the plurality of wires a three-dimensional array of intersection regions; the memory element is in the intersection region, and the memory cells of the three-dimensional array are accessible via the plurality of semiconductor materials and the plurality of wires; and a plurality of conductive conformal structures, each electrically conductive Forming a structure on a different stack of the plurality of stacks; the second plurality of wires are disposed over the plurality of stacks and parallel to the plurality of strips of semiconductor material, each of the second plurality of wires Electrically connecting with the different conductive conformal structures of the plurality of conductive conformal structures; and the third plurality of wires are disposed on the first plurality of wires and parallel to the first plurality of wires, the third plurality Each of the wires is connected to a different one of the second plurality of wires. The memory device of claim 11, further comprising: a decoding circuit coupled to the plurality of semiconductor materials, the first plurality of wires, and the third plurality of wires in the plurality of stacks for accessing The memory cell. The memory device of claim 11, wherein the memory element comprises an anti-fuse. The memory device of claim 11, wherein the memory element comprises a charge storage structure. The memory device of claim 11, wherein the memory cell comprises a buried channel charge storage transistor. The memory device of claim 11, wherein the plurality of semiconductor materials in the plurality of stacks comprise doped semiconductors. The memory device of claim 11, wherein the first plurality of wires comprise a blend Miscellaneous semiconductors. The memory device of claim 11, wherein the memory element comprises a portion of a common layer of memory material between the plurality of stacks and the first plurality of wires. The memory device of claim 11, comprising a tunneling layer, a charge trapping layer and a barrier layer between the plurality of stacks and the first plurality of wires, wherein the tunneling layer and the charge trapping layer And the combination of barrier layers constitutes the memory element in the intersection area. The memory device of claim 11, further comprising a plurality of bit lines arranged on the plurality of stacks and parallel to the plurality of strips of semiconductor material, wherein different bit lines of the plurality of bit lines are via The plurality of bit line contacts and the stepped structure are electrically connected to different planar positions in the plurality of stacks. A method of fabricating a memory device, comprising: forming a plurality of strips of semiconductor material material extending from the integrated circuit substrate, the plurality of stacks comprising at least two elongated semiconductor materials separated by an insulating layer into a plurality of planar locations The plurality of planar positions, the plurality of semiconductor materials sharing the same planar position of the plurality of planar positions are connected to one of the plurality of bit line contacts by a stepped structure, such that the stepped structure a step in the end of the plurality of semiconductor materials; forming a plurality of wires arranged orthogonal to the plurality of stacks, and conforming to the plurality of stacks, such that the surface of the plurality of semiconductor materials Forming a three-dimensional array of intersection regions with the plurality of wire intersections; and forming a memory element in the intersection region, the plurality of semiconductor materials and the plurality of wires establishing access to the three-dimensional array of memory cells. A method of manufacturing a memory device, comprising: Forming a plurality of strips of semiconductor material stack extending out of the integrated circuit substrate, the plurality of stacks including at least two strips of semiconductor material separated by an insulating layer to form different planar positions in a plurality of planar positions, sharing the plurality of planar positions The elongated semiconductor materials in a same planar position are connected to one of the plurality of bit line contacts by a stepped structure, such that the steps in the stepped structure are located in the elongated semiconductor material Forming a first plurality of wires arranged orthogonal to the plurality of stacks and conforming to the plurality of stacks such that a surface of the plurality of semiconductor materials intersects with the plurality of wires a three-dimensional array of intersection regions; forming a memory element in the intersection region, the memory cells of the three-dimensional array accessible by the plurality of semiconductor materials and the plurality of wires; forming a plurality of conductive conformal structures, each a conductive conformal structure over a different stack of the plurality of stacks; forming a second plurality of wires arranged at the plurality of Above the stack, and in parallel with the strips of semiconductor material, each of the second plurality of wires is electrically connected to a different one of the plurality of electrically conductive conformal structures; and forming a third plurality of strips A wire is disposed over the first plurality of wires and parallel to the first plurality of wires, each of the third plurality of wires being coupled to a different one of the second plurality of wires.