KR920009668B1 - Nonvolatile memory system - Google Patents

Abstract

No content.

Description

Nonvolatile Memory Device

1 is a cross-sectional view for explaining a nonvolatile memory device according to a first embodiment of the present invention;

2 is a cross-sectional view for explaining a nonvolatile memory device in accordance with a second embodiment of the present invention;

3 is a cross-sectional view illustrating a conventional nonvolatile memory device.

* Explanation of symbols for the main parts of the drawings

2: source diffusion layer 3a, 3b: drain diffusion layer

4a, 4b: gate oxide film 5a, 5b: floating gate electrode

6a, 6b: tunnel oxide film 7: erase gate (drain electrode)

9a, 9b: control gate electrode 10a, 10b: CVD oxide film

101: semiconductor substrate 102: drain diffusion layer

103a, 103b source diffusion layer 104,104 gate oxide film

105a, 105b: floating gate electrode 106a, 106b: tunnel oxide film

107: erase gate electrode 108a, 108b: insulating film

109a, 109b: control gate electrodes 110a, 110b: CVC oxide film

111: BPSG film

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device, and more particularly to a nonvolatile memory device having two or more layers of gate electrode structures capable of electrically exchanging records.

[Background technology and its problems]

In recent years, a single transistor / cell batch erasing type EEPROM has been attracting attention as a nonvolatile memory device, instead of an ultraviolet erasing type EPROM.

That is, in the EPROM shown in FIG. 3, the source diffusion layer 22 and the drain diffusion layer 23 are formed in the P-type silicon substrate 21. In this case, the junction depth of the source diffusion layer 22 is the junction breakdown voltage. It is formed deep enough to be larger than this erase voltage.

A gate oxide film 24 is formed on the P-type silicon substrate 21 between the source diffusion layer 22 and the drain diffusion layer 23, and the floating gate 25 is formed on the gate oxide film 24. The control gate electrode 27 is formed on the floating gate electrode 25 via the insulating film 26.

Here, the operation mechanism of the batch erasing type EEPROM is made as follows.

First, information recording is performed in the same way as the UV erasure type EPROM by applying a high voltage to the control gate electrode 27 and the drain diffusion layer 23 to inject and accumulate channel hot electrons into the floating gate electrode 25 to raise the threshold of the cell transistor. On the other hand, the erasing of the information is performed by applying a zero voltage to the control gate electrode 27 while applying an erase voltage to the source diffusion layer 22 so that the FN tunneling current flows through the gate oxide film 24, thereby causing the storage electrons to float. It is carried out by releasing from 25 to the source diffusion layer 22.

Since the integrated erasure type EEPROM suffers from the source diffusion layer 22 in the array, the bulk erasure is performed, and the structure realizes almost the same cell area as the ultraviolet erasure type EPROM.

However, in order to set the erase voltage to a practical value, for example, 12.5 [V], the thickness of the gate oxide film 24 needs to be thinned to about 100 GPa, so that the defect of the gate oxide film 24 is increased and productivity is deteriorated. have. In addition, as the gate oxide film 24 becomes thinner, the junction leakage current is mixed in addition to the FN tunneling current when information is erased, so that the stable operation of the memory cell is inhibited or the operating power cannot be realized with a single 5 [V]. have.

As described above, in the conventional nonvolatile memory device, since the thin gate oxide film cannot be used, the reliability of the memory cell cannot be sufficiently increased.

[Purpose of invention]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned general drawbacks, and an object of the present invention is to provide a nonvolatile memory device capable of electrically erasing a single transistor / cell while achieving reliability with an ultraviolet erasing EPROM.

[Configuration of Invention]

In order to achieve the above object, the nonvolatile memory device of the present invention is formed on a first region and a second region in a surface region of a semiconductor substrate, and on a channel between the first region and the second region so as to be electrically floating. A nonvolatile memory device comprising a first gate electrode formed on the first gate electrode and a transistor having a second gate electrode serving as a control gate as a memory cell, wherein the first gate electrode is formed as a memory cell. A second insulating film thinly formed on the sidewall of the electrode and a third electrode formed with the second insulating film interposed between the first gate electrode are provided to supply a potential required to the third electrode as a mechanism for erasing operation. The charge accumulated in the first gate electrode is discharged to the third electrode through the second insulating film.

[Action]

According to such a nonvolatile memory device, electrical recording can be exchanged, and the first insulating film does not need to be thinned to improve the erase characteristics. Accordingly, it is possible to provide a nonvolatile memory device capable of electrically erasing one transistor / cell having higher reliability than a nonvolatile memory device in which the first insulating film must be thinly formed.

In addition, when the second insulating film is formed of an oxide film of polycrystalline silicon, a good oxide film can be formed on the sidewall of the first gate electrode when the heat treatment is performed.

EXAMPLE

Hereinafter, the nonvolatile memory device of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a nonvolatile memory device according to a first embodiment of the present invention, which includes a source diffusion layer 2 and a drain diffusion layer 3a of a memory cell in a surface region of a P-type silicon substrate 1. And 3b), and gate oxide films 4a and 4b are formed on the channel region between the source diffusion layer 2 and the drain diffusion layers 3a and 3b. Floating gate electrodes 5a and 5b are formed on the gate oxide films 4a and 4b, and the tunnel oxide film 6a is located on the side of the source diffusion layer 2 on the sidewalls of the floating gate electrodes 5a and 5b. And 6b are formed, and the erase gate electrode 7 is formed with the tunnel oxide films 6a and 6b interposed between the floating gate electrodes 5a and 5b. The erase gate 7 is electrically connected to the source diffusion layer 2 so that the memory cells become common in the array and also function as a source electrode. The control gate electrodes 9a and 9b are formed on the floating gate electrodes 5a and 5b via the insulating films 8a and 8b, and the insulating films 8a and 5b are formed on the floating gate electrodes 5a and 5b. CVD oxide films 10a and 10b are formed to cover the control gate electrodes 9a and 9b via 8b). A BPSG film 11 is formed on the entire surface thereof, and the BPSG film 11 is provided with a connection hole on the drain diffusion layer 3a. The connection hole provided on the drain diffusion layer 3a is formed through the connection hole. The bit line 12 is formed to be electrically connected to the drain diffusion layer 3a.

Such a nonvolatile memory device is capable of supplying a potential required to the erase gate electrode to release charges from the floating gate to the erase gate through a tunnel oxide film, thereby enabling electrical exchange of records. As an example of the manufacturing method of the nonvolatile memory device, first, as in the conventional batch erasing type EESPROM as shown in the third drawing, a two-layer polysilicon gate electrode is formed, and only a thin sidewall of the floating gate electrode is formed. After forming an insulating film such as a polysilicon oxide film of about 300 Å, a connection hole is formed in the insulating film on the source diffusion layer, and then polycrystalline silicon doped with n-type impurities is deposited on the entire surface.

Then, the polysilicon is patterned so as to remain across the two weed lines, thereby forming an erase gate electrode (source electrode) electrically connected to the source diffusion layer.

According to this configuration, since the erase gate electrode is formed on the sidewall of the floating gate electrode through the tunnel oxide film, the erase gate electrode can be formed separately from the tunnel oxide film and the gate oxide film. Therefore, the tunnel oxide film can be optimized according to the erase voltage.

In the above embodiment, an erase gate electrode electrically connected to the source diffusion layer is formed on the source diffusion layer. However, an erase gate electrode electrically connected to the train diffusion layer may be formed on the drain diffusion layer. The tunnel oxide film on the floating gate electrode side wall is preferably provided on the drain diffusion layer side. The tunnel oxide film may be provided over the other side of the floating gate electrode.

Next, a nonvolatile memory device according to a second embodiment of the present invention will be described.

2 shows a nonvolatile memory device according to a second embodiment of the present invention. The nonvolatile memory device includes a drain diffusion layer 102 and a source diffusion layer 103a of a memory cell on a surface of a P-type silicon substrate 101. 103b is formed, and gate oxide films 104a and 104b are formed on the channel region between the drain diffusion layer 102 and the source diffusion layers 103a and 103b, and the gate oxide film 104a on the drain diffusion layer 102 is formed. Floating gate electrodes 105a and 105b are formed on 104b. Tunnel oxide films 106a and 106b are formed on the sidewalls of the floating gate electrodes 105a and 105b, and the tunnel oxide films 106a and 106b are formed on the sidewalls of the drain diffusion layer 102. An erase gate electrode 107 is formed between the drain diffusion layer 102 so that the erase gate electrode 107 also functions as a drain electrode.

The control gate electrodes 109a and 109b are offset structures on the insulating films 108a and 108b on the floating gate electrodes 105a and 105b and the insulating films 104a and 104b on the source regions 104a and 103b. It is formed to take.

Further, CVD oxide films 110a and 110b are formed to cover the floating gate electrodes 105a and 105b and the control gate electrodes 09a and 109b, and the BPSG films 111 are formed on the entire surface thereof. The film 111 is provided with a connection hole on the drain diffusion layer 102. The bit line 112 is electrically connected to the drain diffusion layer 102 via a connection hole provided on the drain diffusion layer 102.

According to this configuration, since the erase gate electrode is formed on the sidewalls of the floating gate electrodes 105a and 105b through the tunnel oxide film, the gate oxide films 106a and 106b and the gate oxide films 104a and 104b can be formed separately. Therefore, the tunnel oxide films 106a and 106b can be optimized according to the erase voltage. In addition, since the gate oxide films 104a and 104b do not need to be peeled off to improve the erase characteristics, the drain junction breakdown voltage can be sufficiently high. In the present embodiment, the floating gate electrodes 105a, as the source diffusion layer 103a and 103b and the drain diffusion layer 102 are taken from the source diffusion layer on the channel and the control gate electrodes 109a and 109b are formed. When charge is discharged from the 105b) to the erase gate 107, even if the charge is excessively released (overerase), the control gate electrode is present on the channel, thereby preventing the channel from being electrically conductive. The tunnel oxide films 106a and 106b may be provided over the other side surfaces of the floating gate electrodes 105a and 105b.

[Effects of the Invention]

As described above, according to the present invention, it is possible to provide a nonvolatile memory device which can achieve the same reliability as that of an ultraviolet erasing EPROM while being capable of electrically erasing one transistor / cell.

Claims (6)

Between the first region (source diffusion layer; 2) and the second region (drain diffusion layer; 3a, 3b) formed in the surface region of the semiconductor substrate 1, and between the first region 2 and the second region 3a, 3b. A first gate electrode (floating gate electrode 5a, 5b) formed on the channel region of the substrate to be electrically floating, and formed on the first gate electrode 5a, 5b via a first insulating film to form a control gate. In a nonvolatile memory device using a transistor having a functioning second gate electrode (9a, 9b) as a memory cell, a second insulating film (tunnel oxide film) formed on sidewalls of the first gate electrode (5a, 5b); 6b), the second insulating films 6a and 6b, and the second insulating films 6a and 6b are formed between the first gate electrodes 5a and 5b to form the first region 2 or the first electrode. A nonvolatile memory device, characterized in that a third electrode (erasure gate electrode) 7 is provided which is electrically connected to one of the two regions 3a and 3b. The method of claim 1, wherein the electric charges stored in the first gate electrode (floating gate electrode) 5a, 5b by supplying a potential required to the third electrode (erasure gate electrode) 7 are transferred to the second insulating layer 6a, 6b. And (e) to discharge the writes electrically to the third electrode (7). The nonvolatile memory device according to claim 1, wherein the second insulating film (tunnel oxide film; 6a, 6b) is formed of a polycrystalline silicon oxide film. Between the first region (drain diffusion layer) 102 and the second region (source diffusion layer; 103a, 103b) formed in the surface region of the semiconductor substrate 101, and between the first region 102 and the second region 103a, 103b. A first gate electrode (floating gate electrode 105a, 105b) formed on a channel region in contact with the first region 102 in U and is electrically floating, and formed on the first gate electrode 105a, 105b. A transistor having a second gate electrode (control gate electrode 9a, 9b) formed in a substrate insulating film positioned on a channel region in contact with the insulating film and the second regions 103a and 103b and serving as a control gate is used as a memory cell. In the nonvolatile memory device, second insulating films (tunnel oxide films) 106a and 106b formed on sidewalls of the first region 102 with respect to the first gate electrodes 105a and 105b and the second insulating films 106a and A third electric field formed between the first gate electrodes 5a and 5b and electrically connected to the first region 102. (Erase gate electrode; 107), the non-volatile memory device, characterized in that it is installed. 5. The method of claim 4, wherein charges accumulated in the first gate electrode (floating gate electrode 105a, 105b) by supplying a potential required to the third electrode (erasure gate electrode; 107) are transferred to the second insulating film (tunnel oxide film; A nonvolatile memory device, characterized in that electrical exchange of records is carried out by discharging to the third electrode (107) via 106a, 106b. 5. The nonvolatile memory device according to claim 4, wherein the second insulating films (tunnel oxide films) 106a and 106b are formed of polysilicon oxide films.

Images