JPH0917795A - Bump structure - Google Patents

Abstract

PURPOSE: To provide a solder bump structure which can be protected against cracking, restrained from being separated from a board electrode due to a thermal stress applied after a flip chip is mounted, and manufactured at a low cost. CONSTITUTION: A bump structure is formed on the electrode of a flip chip semiconductor device, wherein the bump structure is composed of a barrier metal 2 laminated on an electrode pad 1 of a semiconductor device, metal columns 3 provided upright on the barrier metal 2, a core bump 4 laminated spreading over the metal columns 3, and a solder bump 5 laminated on the core bump 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of metal bumps used for flip chips.

[0002]

2. Description of the Related Art FIG. 6 shows an example of bumps in a conventional flip chip. This diagram is a schematic view, and is different from the actual size. Reference numeral 6 in the drawing denotes a semiconductor substrate, in which an electronic circuit (not shown) is monolithically formed, and an electrode pad 1 for electrical connection to the outside is formed on one surface.
Are formed. The electrode pad 1 is mainly made of Al (aluminum), and its periphery is surrounded by a part of an insulating protective film 7 made of SiO ₂ (silicon oxide) or SiN (silicon nitride) formed by a CVD method and a photo process, and a part thereof. The barrier metal 2 is exposed and the exposed portion is covered with the barrier metal 2. The barrier metal 2 is a multi-layer metal film, and generally, the lower layer is Cr (chromium) as a diffusion prevention layer that prevents the formation of intermetallic compounds.
And Ti (titanium) and the like, and the upper layer is made of Cu (copper) and Ni (nickel) which have good wettability with solder. Further, solder bumps 5 made of Sn (tin) -Pb (lead) based solder are formed on the barrier metal 2.

The flip chip having the solder bumps 5 as described above is mounted on the mounting substrate 1 as shown in the schematic view of FIG.
It is surface-mounted on CC by CCB (Controlled Collapse Bonding) method. That is, the board electrodes 11 formed on the mounting board 10 and the solder bumps 5 formed on the flip chip are aligned and brought into contact with each other, and the solder bumps 5 are melted by reflowing or the like to be electrically connected. .

[0004]

In the bump structure as described above, when a thermal stress such as a temperature cycle is applied after the flip chip mounting, the solder bumps are not formed due to the mismatch of the thermal expansion coefficient between the semiconductor substrate and the mounting substrate. In some cases, stress was concentrated on the surface of the substrate, causing cracks, and bumps were separated from the substrate electrodes, leading to reliability problems. In order to prevent this, there is a method of injecting a resin between the semiconductor substrate and the mounting substrate to reduce the concentration of stress on the bumps, but this increases the cost. An object of the present invention is to solve these problems and provide a bump structure that is inexpensive and has high reliability.

[0005]

In order to achieve the above object, the present invention has a structure of a bump formed on an electrode portion of a flip-chip type semiconductor device, and a barrier metal laminated on an electrode pad of the semiconductor device. It is characterized by comprising a plurality of metal pillars standing on the barrier metal, core bumps laminated over the plurality of metal pillars, and solder bumps laminated on the core bumps.

[0006]

With this configuration, the bonding strength between the bump and the electrode pad and the mounting substrate electrode is the same as that of the bump having the conventional structure, but stress such as temperature cycle is absorbed by the deformation of the ductile thin metal column. In this way, cracks in the bumps and peeling from the substrate electrodes can be prevented.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view schematically showing the outline of an embodiment of the present invention. In this figure, the same reference numerals as those in FIGS. 5 and 6 indicate the same or corresponding ones, and 3 is composed of a plurality of Cu. Metal pillars 4 are C formed over a plurality of metal pillars 3.
Core bumps 5 made of u are Sn—Pb based solder bumps formed on the core bumps 4. FIG. 2 is a diagram schematically showing an outline of the manufacturing process of the embodiment of FIG. An Al thin film having a thickness of about 1 μm deposited on one surface by electron beam evaporation is patterned by a photo process, and a part thereof is used as an electrode pad 1 (FIG. 2a). Then, a SiN film is deposited on the surface to a thickness of about 1 μm, and a contact hole is formed by a photo process while leaving the SiN film overlapping the peripheral edge of the electrode pad 1 to form an insulating protective film 7 (FIG. 2b). After this, Cr,
Cu is sputtered in this order to form a barrier metal layer 2a having a thickness of several thousand angstroms, and a photoresist 8 is spin-coated thereon to a thickness of about 30 μm (FIG. 2).
c). Next, the photoresist 8 is patterned as shown in FIG. 2d, electrolytic plating of Cu is performed by using the barrier metal layer 2a formed previously as a power feeding layer, a plurality of metal columns 3 are formed, and electrolytic plating is further continued to form a plurality of metallic columns. The core bump 4 grown over the metal pillar 3 is formed. Next, electrolytic plating of solder is performed again using the barrier metal layer 2a as a power supply layer to form the solder bumps 5 (FIG. 2e). After that, the resist 8 is peeled off, the barrier metal layer 2a is selectively etched, and then the solder is once melted in an inert atmosphere to obtain the final shape shown in FIG.

With such a structure, it is possible to connect to a printed circuit board by the CCB method. FIG. 3 shows the state at that time. This figure is also a schematic representation and differs from the actual size. Reference numeral 10 denotes a mounting board, and 11 denotes a board electrode for connection formed on the mounting board 10. When temperature stress is applied in this state, the mounting substrate having a large expansion coefficient generally expands and contracts more than the semiconductor substrate, and the stress concentrates on the bonded bump portions. This stress is applied to a plurality of metal columns 3
The stress applied to the portion of the solder bump 5 due to the deformation of the portion can be reduced. 4 and 5 show examples of cross sections of the metal columns. FIG. 4 shows a plurality of metal columns having a circular cross section and arranged at equal pitches.
For example, the diameter of the metal columns is 10 μm and the pitch is 30 μm.
As a result, good results can be obtained by forming 25 pieces. FIG. 5 shows a metal column having a cross section that is elongated in the vertical direction of the paper and in which a plurality of metal columns are repeatedly arranged in the horizontal direction of the paper. It is difficult to absorb the stress in the vertical direction of the paper but absorb the stress in the horizontal direction. Moreover, the strength is stronger than that of the example of FIG. For example, the size of the metal columns in this case is 10 μm × 80 μm, and good results can be obtained by forming five metal columns with a pitch of 30 μm. Various other examples of the shape of the metal column can be considered, but as long as they are made of a plurality of thin metals to have ductility and support one core bump, they do not depart from the gist of the present invention.

[0009]

As described above, since the thermal stress can be absorbed, flip-chip mounting can be performed even when the difference in thermal expansion coefficient between the mounting substrate and the semiconductor substrate is large. Therefore, according to the present invention, it is possible to provide a flip chip having a larger chip size than in the past, and it is remarkable to contribute to the provision of a flip chip capable of larger processing. Further, there is no need to pour resin between the substrates to relieve the stress, and the cost can be reduced by reducing the mounting process.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram schematically showing a manufacturing process of the embodiment of FIG.

FIG. 3 is a diagram showing a mounted state of a flip chip to which the embodiment of FIG. 1 is applied.

FIG. 4 is a diagram showing an example of a cross section of a metal column of the present invention.

FIG. 5 is a diagram showing another example of the cross section of the metal column of the present invention.

FIG. 6 is a view showing an example of a conventional flip-chip bump structure.

7 is a diagram showing a mounted state of a flip chip to which the example of FIG. 6 is applied.

[Explanation of symbols]

 1 electrode pad 2 barrier metal 3 metal pillar 4 core bump 5 solder bump 6 semiconductor substrate 7 insulating film

Claims (1)

[Claims] 1. A structure of a bump formed on an electrode part of a flip-chip type semiconductor device, comprising: a barrier metal laminated on an electrode pad of the semiconductor device; a plurality of metal pillars standing on the barrier metal; A bump structure comprising a core bump laminated on a plurality of metal columns and a solder bump laminated on the core bump.