JPH0646398A - Image data compression method - Google Patents

Abstract

(57) [Summary] [Object] To provide a method of reducing block distortion that occurs when an image compressed for each pixel block is reproduced, and image data compression of this type is performed over a plurality of consecutive frames. An object of the present invention is to provide a method for reducing the distortion between the blocks, which becomes noticeable when appearing at the same position in a moving image (a still image is updated at a speed of 30 sheets / second to be a moving image). To do. A method for compressing an image data in which a compression target image of one frame or one field is divided into a plurality of blocks, pixels included in each block are linearly transformed, and the transform coefficient is quantized and transmitted. The conversion target block is different for each frame or field for a plurality of continuous frames or fields, and linear conversion is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to image data which is obtained by dividing an image to be compressed of one frame into a plurality of blocks, linearly transforming the pixels contained in each block, and quantizing the transform coefficient. Regarding the compression method, for example, video conferencing / videophone, compression / improvement of data transmission and storage efficiency for image data such as color still images, especially color moving images
The present invention relates to an image data compression method used for a device having a decompression function and a device contributing to AVCC (audio / visual / computer / communication) fusion.

[0002]

2. Description of the Related Art As a conventional image data compression method, a unit block is composed of pixels at exactly the same position for each frame, and linear conversion is performed for each unit block. Here, as the linear transformation, there is a discrete cosine transformation found in the JPEG method. For example, as shown in FIG. 3, when a unit block is composed of 8 × 8 pixels, with respect to the address (m, n) of the pixels composing the frame,
64 pixels from (1,1) to (8,8), (1,9)
The addresses of the pixels constituting the block are fixed, such as 64 pixels from (8, 16) to (8, 16).

[0003]

However, the above-mentioned prior art has the following drawbacks. Not limited to DCT, generally, if high-efficiency coding is performed to reduce the average number of bits per pixel or if the compression rate is increased, the conversion outputs in the blocks are all linearly summed when the pixels are inversely converted and reproduced. Although this causes deterioration of image quality, there is a drawback that distortion occurs between adjacent blocks at this time, resulting in a discontinuous and unsightly image. In particular, for a moving image in which image data compression of this type is performed over a plurality of consecutive frames (a still image is updated at a speed of 30 images / second to be a moving image), the blocks between blocks are reproduced. Since the distortion appears in the same position, the distortion becomes noticeable, and it is more noticeable and extremely unsightly than when viewing a still image with interblock distortion. Therefore, it may be difficult to perform processing such as increasing the compression rate. An object of the present invention is to eliminate the above-mentioned conventional drawbacks.

[0004]

In order to achieve this object, the characteristic configuration of the image data compression method according to the present invention is as follows.
An image data compression method in which an image to be compressed of a frame or one field is divided into a plurality of blocks, pixels included in each block are linearly transformed, and the transform coefficient is quantized and transmitted. It is configured such that the conversion target block is different for each frame or field and the linear conversion is performed on the frame or field.

[0005]

The position of the distortion generated between the adjacent blocks of the reproduced image is dispersed to reduce the effect that the distortion appears to be emphasized due to the inter-block distortion occurring at the same position.

[0006]

Therefore, according to the present invention, even when the high-efficiency coding is performed to reduce the average number of bits per pixel or the compression rate is increased, the block distortion generated in the reproduced image in the moving image causes It has become possible to provide an image data compression method capable of reducing discontinuous discomfort.

[0007]

Embodiments of the image data compression method according to the present invention will be described below. The color moving image displays a plurality of still images on a commercial television at 30 frames / second, and more specifically, a still image of one frame is divided into an even field and an odd field, and two fields are displayed at 1/60 second per field. Is configured. Therefore, image processing such as compression / expansion of a moving image
Alternatively, it can be handled as image processing such as compression / expansion for still images in each field. Therefore, image processing such as compression / expansion of moving images will be described below as image processing for handling color still images. As shown in FIG. 1, the image compression / reproduction means 1 in the image processing apparatus outputs an image buffer 2 for storing one frame of image data and the data in the image buffer 2 for each unit block of 8 × 8 pixels. A block generation unit 8, an orthogonal transformer 3 that performs orthogonal transformation on the unit block, a quantizer 4 that quantizes the transformed output, a Huffman coded quantized data, and a code / decode that performs the inverse operation. It comprises a device 5, a compressed data buffer 6 for storing encoded data, and a controller 7 for controlling their operation.

The image buffer 2 is composed of a high-speed semiconductor memory and has a capacity capable of storing one frame of raster data composed of at least M rows × N columns of pixels as input image data. The block generator 8 divides and outputs the image data stored in the image buffer 2 into blocks each having 8 × 8 pixels, and stores the reproduced image data in the image buffer 2 in reverse. The counter circuit 8a determines the start addresses of the pixels to be divided into blocks in the row and column directions, the address generation circuit 8b determines the start address of each block based on the value of the counter circuit 8a, and the address generation circuit 8b. The access circuit 8c takes out address data from the image buffer 2 and outputs it to the orthogonal transformer 3. As shown in FIG. 2, the output is divided into unit blocks configured by changing the address for each pixel in the range of 8 pixels for each frame or field. That is, for the pixel address (m, n), when the value of the counter circuit 8a is 0, 64 pixels from (1, 1) to (8, 8), (1, 9) to (8, 16) Up to 64 pixels, and when the value of the counter circuit 8a is 1, 64 pixels from (2, 2) to (9, 9), (2, 10) to (9, 17) Each time the value of the counter circuit 8a is incremented by 1, the address generator circuit 8b is composed of a block of 64 pixels.
The block start address is incremented by 1 in the row and column directions, and when the value of the counter circuit 8a reaches 7, the value of the counter circuit 8a is reset to 0 and the next time from (1, 1) to (8, 8 A series of operations is repeated so that 64 pixels up to the above) becomes a unit block. On the contrary, the data inversely transformed by the orthogonal transformer 3 is the address generating circuit 8 according to the value of the counter circuit 8a which is set in advance according to the data (instruction from the controller 7) indicating the block division.
It is stored in the address determined by b via the access circuit 8c.

The orthogonal transformer 3 has a D block for each pixel block.
Perform CT (discrete cosine transform) and inverse DCT (inverse discrete cosine transform). The quantizer 4 quantizes the transformed output according to a quantization table which is set in advance and determines a compression rate, and then performs zigzag scanning in which two-dimensional coefficients are arranged in one dimension and vice versa. The encoder / decoder 5 converts the one-dimensional quantized data into Huffman code and performs the inverse operation.

The controller 7 has basic data necessary for image compression / reproduction (for example, setting values of the counter circuit 8a, orthogonal transformation table, quantized data, etc.).
To the transmission partner together with the compressed data, or to extract basic data from the data received from the transmission partner and output them to the functional blocks such as the block generator 8 and the quantizer 4. It controls the data processing procedure and timing for compression / reproduction.

Another embodiment of the present invention will be described below. In the above embodiment, an example in which the process of increasing the start address of the divided block by 1 in the row and column directions is repeatedly performed for 8 consecutive frames or 8 fields has been described, but the present invention is not limited to this. Instead, it can be set appropriately. For example, after the process of increasing the start address of the divided block by 1 in the row and column directions is performed on 8 consecutive frames or 8 fields, the next 8 consecutive
For frames or 8 fields, the reverse direction, ie
The processing may be performed so as to decrease by 1 in the row and column directions, that is, the position of the block may reciprocate, or the start address of the divided block may be increased by 2 in the row and column directions. However, the block head address may be randomly set.

In the above embodiment, the description has been made of the case where the process of changing the start address of the divided block is performed for continuous 8 frames or 8 fields. However, in the case of a field, an even field forming the same frame is used. And the start address of the block of the odd field may be the same, or the start address of the block divided for every plural fields may be changed.

In the above embodiment, the unit block to be divided is composed of 8 × 8 pixels, but the size of the unit block is not limited to this and may be an arbitrary value K. . In this case, for example, the process of increasing the start address of the divided block by 1 in the row and column directions is performed for continuous K frames or K fields.

The configuration of the circuit block described in the above embodiment is not limited to this, and can be arbitrarily configured by using a known technique.

It should be noted that reference numerals are added to the claims for convenience of comparison with the drawings, but the present invention is not limited to the configurations of the accompanying drawings by the entry.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an image processing apparatus.

FIG. 2 is an explanatory diagram of blocking.

FIG. 3 is an explanatory diagram of block formation showing a conventional example.

[Explanation of symbols]

 1 image compression / reproduction means 2 image buffer 2 3 orthogonal transformer 4 quantizer 5 encoder / decoder 6 compressed data buffer 7 controller 8 block generator

Claims (1)

[Claims] 1. A method for compressing an image data in which an image to be compressed in one frame or one field is divided into a plurality of blocks, pixels included in each block are linearly transformed, and the transform coefficient is quantized and transmitted. An image data compression method configured to perform linear conversion on a plurality of continuous frames or fields by changing the conversion target block for each frame or field.