JP2008304426A - Arbitrary waveform generator and semiconductor test equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an optional waveform generator and semiconductor test apparatus that can shorten the test time and acquire analog voltage where error voltage by divergence from the linearity of an output signal of a D/A converter is accurately corrected. <P>SOLUTION: The optional waveform generator comprises a D/A converter of a rough adjustment output system and a fine adjustment output system that have the same characteristic and are driven by a common clock, a timing adjusting means for delaying, by one clock, digital data to be input into the D/A converter of the rough adjustment output system, a data correcting section in which the calibration data for correcting the output error voltage of the D/A converter of the rough adjustment output system is written so as to be digital data to be input into the D/A converter of the fine adjustment output system using, as address, the digital data to the theoretical value of the D/A converter of the rough adjustment output system, and an adder for adding the output voltage of the D/A converter of the rough adjustment output system and the output voltage of the D/A converter of the fine adjustment output system. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an arbitrary waveform generator and a semiconductor test apparatus, and more particularly to calibration of an output signal.

  For example, in a semiconductor test apparatus that tests a measurement target IC (hereinafter referred to as a DUT) configured to output a multi-gradation voltage such as a liquid crystal driving IC, a highly accurate multi-gradation voltage is output as an expected voltage. An arbitrary waveform generator is used.

  FIG. 6 is a block diagram showing an example of such a semiconductor test apparatus. The DUT 1 is a liquid crystal driving IC configured to output a multi-gradation voltage from a plurality of output pins, and each output pin is connected to one input terminal of the plurality of comparators 2. The arbitrary waveform generator 3 is configured to output a highly accurate multi-gradation voltage as an expected voltage corresponding to the multi-gradation voltage output from the DUT 1, and its output terminal is the other of the comparator 2. Connected to the input terminal. The output terminals of these comparators 2 are connected to the determination unit 4.

  An output voltage test for each output pin of the DUT 1 will be described. Each output pin of the DUT 1 outputs a multi-gradation voltage Vout corresponding to the digital data Din as shown in FIG. 7, and the arbitrary waveform generator 3 also has a multi-gradation so as to be synchronized with the output voltage change of each output pin of the DUT 1. Output the expected voltage. The comparator 2 compares the output voltages of the DUT 1 and the arbitrary waveform generator 3 and outputs the comparison results to the determination unit 4. The determination unit 4 determines the quality of the DUT 1 based on the comparison result of the comparator 2.

  FIG. 8 is a block diagram of the arbitrary waveform generator 3 that outputs such a multi-grayscale expected voltage. The arbitrary waveform generator 3 includes a D / A converter 31 and an output adjustment unit 32.

  FIG. 9 is an example of output characteristics of the arbitrary waveform generator 3 configured as shown in FIG. The analog voltage Vout output corresponding to the digital data Din input to the D / A converter 31 desirably varies linearly as indicated by the ideal straight line A in FIG. In many cases, the output characteristic B shows a non-linear characteristic deviating from the ideal straight line A.

  The deviation of the non-linear characteristic from the ideal straight line A is that the output setting resolution of the analog voltage Vout is in units of 1 LSB which is the resolution of the digital data Din, but the analog corresponding to the increase / decrease of the digital data Din per 1 LSB. It is generated because the output of the voltage Vout does not necessarily increase or decrease uniformly.

  If the output of the analog voltage Vout deviates from the ideal straight line A by 1 LSB or more as shown in (B), the setting of the digital data Din is changed so as to correct the error voltage due to the deviation. Thus, the output of the analog voltage Vout can be calibrated in LSB units.

  In the configuration of FIG. 8 as well, the output adjustment unit 32 can compress some non-linear characteristic deviation, but it cannot be said to be an accurate linearity calibration.

JP 2002-131398 A

  Patent Document 1 describes a voltage generator configured to generate a high-precision multi-grayscale voltage by using a high-precision D / A converter and a low-precision D / A converter. .

  In recent DUT tests by a semiconductor test apparatus, for example, with an increase in gradation of a liquid crystal display element, an output of an analog voltage Vout in which an error voltage is corrected with high accuracy is required even for a deviation of 1 LSB or less.

  By using the voltage generator described in Patent Document 1, an output signal in which the error voltage due to the divergence is corrected with high accuracy can be obtained. However, a high accuracy D / A converter and a low accuracy D / A conversion are obtained. No mention is made of matching the output timing of the units in units of clocks. Therefore, if both output signals are shifted in time, the determination result must be output after waiting until both output signals become stable, which makes it difficult to shorten the test time. is there.

  The present invention pays attention to such a conventional problem, and the purpose thereof is to perform D / A conversion by outputting the output signals of the two systems of D / A converters in a clock unit without time lag. Another object of the present invention is to provide an arbitrary waveform generator and a semiconductor test apparatus capable of obtaining an analog voltage in which an error voltage due to a deviation from the linearity of the output signal of the detector is corrected with high accuracy and reducing a test time.

The invention of claim 1 which achieves such a problem,
A coarse adjustment output system and a fine adjustment output system D / A converter having the same characteristics and driven by a common clock;
Timing adjustment means for delaying digital data input to the D / A converter of the coarse adjustment output system by one clock;
D / A conversion of the fine adjustment output system with the calibration data for correcting the output error voltage of the D / A converter of the coarse adjustment output system as digital data corresponding to the theoretical value of the D / A converter of the coarse adjustment output system A data correction unit written to be digital data input to the device,
An arbitrary waveform generator comprising an adder for adding and outputting an output voltage of a D / A converter of a coarse adjustment output system and an output voltage of a D / A converter of a fine adjustment output system.

  According to a second aspect of the present invention, in the arbitrary waveform generator according to the first aspect, an amplification factor of the fine adjustment output system of the adder is set smaller than an amplification factor of the coarse adjustment output system.

The invention of claim 3 is a semiconductor test apparatus in which an output of an arbitrary waveform generator is applied to a DUT via a test head and a performance board.
The arbitrary waveform generator is
A coarse adjustment output system and a fine adjustment output system D / A converter having the same characteristics and driven by a common clock;
Timing adjustment means for delaying digital data input to the D / A converter of the coarse adjustment output system by one clock;
The D / A conversion of the fine adjustment output system is based on the assumption that the calibration data for correcting the output error voltage of the D / A converter of the coarse adjustment output system is the digital data corresponding to the theoretical value of the D / A converter of the coarse adjustment output system. A data correction unit written to be digital data input to the device,
The output voltage of the D / A converter of the coarse adjustment output system and the adder for adding and outputting the output voltage of the D / A converter of the fine adjustment output system are characterized.

  According to a fourth aspect of the present invention, in the semiconductor test apparatus according to the third aspect, the amplification factor of the fine adjustment output system of the adder of the arbitrary waveform generator is set smaller than the amplification factor of the coarse adjustment output system. Features.

  According to a fifth aspect of the present invention, in the semiconductor test apparatus according to the third or fourth aspect, the arbitrary waveform generator performs calibration including an error voltage at an arbitrary connection point from the arbitrary waveform generator to the input terminal of the DUT. It is characterized by performing.

  As a result, the output signals of the two D / A converters are output without a time lag in units of clocks, so that the error voltage due to the deviation from the linearity of the output signal of the D / A converter can be accurately detected. A corrected analog voltage can be obtained, and an arbitrary waveform generator and a semiconductor test apparatus that can shorten the test time can be realized.

  Hereinafter, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an arbitrary waveform generator according to the present invention. In FIG. 1, digital data Din is input to a D / A converter 102 via a data latch unit 101. The analog voltage converted and output from the D / A converter 102 is input to one input terminal of the adder 103. The digital data Din is also input to the D / A converter 105 via the data correction unit 104. The analog voltage converted and output from the D / A converter 105 is input to the other input terminal of the adder 103.

  The data latch unit 101, the D / A converter 102, the data correction unit 104, and the D / A converter 105 are driven synchronously based on a common clock CLK. The adder 103 adds the analog voltage converted and output from the D / A converter 102 and the analog voltage converted and output from the D / A converter 105, and outputs the result as an analog voltage Vout.

  Since the circuit of FIG. 1 is synchronously driven based on a common clock CLK, the setting data of the D / A converter 102 is input in a state delayed by one clock by the timing adjusting means including the data latch unit 101. Since the setting data of the D / A converter 105 is input in a state delayed by one clock by the reading of the data correction unit 104, the error of the setting data of the D / A converter 102 is determined by the D / A converter 105. The data is corrected by the setting data, and the continuously calibrated data can be continuously transmitted by the same algorithm, whereby the dynamically calibrated data can be continuously transmitted.

  The D / A converter 102 and the D / A converter 105 have the same characteristics, the D / A converter 102 functions as a coarse adjustment output system, and the D / A converter 105 functions as a fine adjustment output system. Let When adding the coarse adjustment output system and the fine adjustment output system by the adder 103, the gain of the fine adjustment output system is made lower than that of the coarse adjustment output system to reduce the resolution of the output voltage of the coarse adjustment output system. Make it high.

  FIG. 2 is a circuit diagram showing a specific example of the adder 103. The output voltage of the D / A converter 102 is input to the operational amplifier OP via the resistor Ra (= R1), and the output voltage of the D / A converter 105 is input to the operational amplifier OP via the resistor Rb (= R2). Is done. A feedback resistor Rc (= R1) is connected between the input terminal and the output terminal of the operational amplifier OP. Here, by setting the resistance values of the resistors R1 and R2 to R2 = 10 × R1, for example, the amplification factor of the fine adjustment output system can be set to 1/10 times the amplification factor of the coarse adjustment output system. Thus, although the fine adjustment output system has a smaller output voltage variable range than the coarse adjustment output system, the fine adjustment output system can output with 1/10 finer accuracy than the coarse adjustment output system.

  By simultaneously driving the D / A converter 102 and the D / A converter 105 and adding and outputting the analog output, the analog output of any value becomes a highly accurate output voltage. Then, by using D / A converters having the same characteristics as the D / A converter 102 and the D / A converter 105 to equalize the input timing on the digital side, the analog output voltage also becomes the same timing, and the analog output waveform is Timing errors can be minimized, and high-quality clean analog output waveforms can be obtained.

As the D / A converter 102 of the coarse adjustment output system, for example, the following is used.
Digital data input range: 0 to 100
Analog output range for digital data: -5V to + 5V
Resolution per 1LSB of digital data: 100mV
From these, the digital data when setting the output voltage 0V is 50, and the digital data when setting the output voltage 1V is 60.

For example, the following is used as the D / A converter 105 of the fine adjustment output system.
Digital data input range: 0 to 100
Analog output range for digital data: -0.5V to + 0.5V
Resolution per digital data 1LSB: 10mV
Accordingly, the digital data when the output voltage 0V is set is 50, and the digital data when the output voltage 0.1V is set is 60.

  A specific operation will be described. It is assumed that the digital data for outputting 3.0 v as a theoretical value is 100 mV with a resolution of 1 LSB of the D / A converter 102 of the coarse adjustment output system. Assume that the relationship between the input digital data and the actually measured value of the output analog voltage Vout in the D / A converter 102 is 2.944v at 80 and 3.044v at 81. Conventionally, 3.044v closest to the theoretical value of 3.0v is the nominal 3.0v output, and 81 is the digital setting data. The error voltage due to the deviation from the theoretical value 3.0v at this time is 0.044v.

  In the present invention, fine calibration is performed using the D / A converter 105 of the fine adjustment output system. In the case of this embodiment, the D / A converter 105 of the fine adjustment output system can set the resolution of 1 LSB to 10 mV, which is 10 times smaller than the D / A converter 102 of the coarse adjustment output system. Therefore, the digital data input to the D / A converter 105 of the fine adjustment output system is arbitrarily increased or decreased, and the analog output voltage is added to the analog output voltage of the D / A converter 102 of the coarse adjustment output system. As a technique, digital data is arbitrarily increased or decreased to obtain a digital data value that is closer to 3.000v from 3.044v. In this case, since it can be set to a minimum of 10 mV, 40 mV may be subtracted to set it to 3.0 V at the D / A converter 105 of the fine adjustment output system, and −4 may be set with digital data. Therefore, the digital setting data of the D / A converter 105 of the fine adjustment output system is 46.

  For example, when it is desired to set the analog output voltage 3.0 v, the digital data 81 is set in the D / A converter 102 of the coarse adjustment output system, and the digital data 46 is set in the D / A converter 105 of the fine adjustment output system. By doing so, an analog output voltage of 3.004v can be obtained. The deviation from the theoretical value of 3.0 v at this time is 0.004 v, and high accuracy can be realized.

  Here, the data correction unit 104 assumes that the calibration data for each setting value of the D / A converter 102 of the coarse adjustment output system is digital data for the theoretical value of the D / A converter 102 of the coarse adjustment output system. Then, the output value is written so as to become calibration data. For example, when + 3.0v is set as described above, D / A converter 102 = 81 and D / A converter 105 = 46 are written.

  FIG. 3 is an explanatory diagram of calibration by adding analog output voltages of the D / A converter 102 and the D / A converter 105, and FIG. 4 is a list of relations between these calibration operations.

  When the digital data 79 is set to the D / A converter 102 of the coarse adjustment output system at the theoretical voltage +2.8 v, the analog output voltage is set to 2.857 v, and the digital data is input to the D / A converter 105 of the fine adjustment output system. Assuming that the single analog output voltage when setting 44 is −0.06 v, an analog output voltage of 2.797 v can be obtained by adding both voltages, and an error voltage due to a deviation from the theoretical voltage +2.8 v Becomes 0.003v.

  When the digital data 80 is set to the D / A converter 102 of the coarse adjustment output system at the theoretical voltage +2.9 v, the analog output voltage is 2.944 v, and the digital data is input to the D / A converter 105 of the fine adjustment output system. Assuming that the single analog output voltage when setting 46 is -0.04v, an analog output voltage of 2.904v can be obtained by adding both voltages, and the error voltage due to the deviation from the theoretical voltage + 2.9v Becomes −0.004v.

  When the digital data 81 is set in the D / A converter 102 of the coarse adjustment output system at the theoretical voltage +3.0 v, the analog output voltage is set to 3.044 v, and the digital data is input to the D / A converter 105 of the fine adjustment output system. Assuming that the single analog output voltage when setting 46 is -0.04v, an analog output voltage of 3.004v can be obtained by adding both voltages, and an error voltage due to a deviation from the theoretical voltage of 3.0v Becomes −0.004v.

  When the digital data 82 is set in the D / A converter 102 of the coarse adjustment output system at the theoretical voltage +3.1 v, the analog output voltage is set to 3.094 v, and the digital data is input to the D / A converter 105 of the fine adjustment output system. Assuming that the single analog output voltage when 61 is set is 0.11v, the analog output voltage of 3.204v can be obtained by adding both voltages, and the error voltage due to the deviation from the theoretical voltage 3.1v is -0.004v.

  Thus, by providing the data correction unit 104 and writing the correction data therein, the digital data of the coarse adjustment output system D / A converter 102 and the D / A converter 105 of the fine adjustment output system are originally processed as software. The digital data of the D / A converter 105 of the fine adjustment output system can be obtained only by inputting the digital data of the D / A converter 102 of the coarse adjustment output system. It is possible to provide simultaneously, and it is possible to obtain a high-accuracy and beautiful waveform output without increasing the software processing load.

  In recent years, the memory capacity of the FPGA has been increased and the operation speed has been increased. Therefore, by using the memory area of the FPGA, a mounting area can be secured and high speed operation can be expected.

  In the above embodiment, an example in which a voltage measuring device is connected to the output terminal of the arbitrary waveform generator and the error voltage up to the output terminal is calibrated has been described. However, when the arbitrary waveform generator is incorporated in a semiconductor test apparatus and used As shown in FIG. 5, the error voltage at the desired point can be calibrated by connecting the voltage measuring device to the desired point of the semiconductor test apparatus and measuring the error voltage.

  FIG. 5 is a block diagram showing a specific example of a semiconductor test apparatus incorporating an arbitrary waveform generator 3 configured as shown in FIG. The output of the arbitrary waveform generator 3 is applied to the DUT 1 via the test head 5 and the performance board 6.

  Here, by connecting the voltage measuring device 7 to the connection point between the test head 5 and the performance board 6 and measuring the voltage at the connection point, the error voltage from the arbitrary waveform generator 3 to the input terminal of the performance board 6 is included. Calibration can be performed, and the error voltage from the arbitrary waveform generator 3 to the input terminal of the DUT 1 is included by measuring the voltage at the connection point by connecting the voltage measuring device 7 to the connection point of the performance board 6 and the DUT 1. Since calibration can be performed, not only the arbitrary waveform generator 3 but also the measurement accuracy of the entire semiconductor test apparatus can be improved.

  As described above, according to the present invention, since the output signals of the two systems of D / A converters are output without time lag in units of clocks, the linearity of the output signals of the D / A converters can be reduced. An analog voltage in which the error voltage due to the deviation is corrected with high accuracy can be obtained, and an arbitrary waveform generator and a semiconductor test device that can shorten the test time can be realized, and a multi-gradation voltage such as a liquid crystal driving IC is output. It is suitable for the test of the DUT configured as described above.

1 is a block diagram showing an embodiment of an arbitrary waveform generator according to the present invention. FIG. FIG. 3 is a circuit diagram showing a specific example of an adder 103 used in FIG. 1. It is calibration explanatory drawing by each analog output voltage addition of D / A converter of 2 systems. FIG. 4 is a list of relationships of calibration operations in FIG. 3. It is a block diagram which shows the specific example of the semiconductor test apparatus incorporating the arbitrary waveform generator 3 based on this invention. It is a block diagram which shows an example of the conventional semiconductor test apparatus. It is an output waveform example figure of a multi-gradation voltage. It is a block diagram of the arbitrary waveform generator which outputs the multi-grayscale expected voltage. FIG. 9 is an example of output characteristics of an arbitrary waveform generator configured as shown in FIG. 8.

Explanation of symbols

1 DUT
2 Comparator 3 Arbitrary Waveform Generator 4 Judgment Unit 5 Test Head 6 Performance Board 7 Voltage Measuring Device 101 Data Latch Unit 102 Coarse Adjustment Output System D / A Converter 103 Adder 104 Data Correction Unit 105 Fine Adjustment Output System D / A converter

Claims (5)

A coarse adjustment output system and a fine adjustment output system D / A converter having the same characteristics and driven by a common clock;
Timing adjustment means for delaying digital data input to the D / A converter of the coarse adjustment output system by one clock;
D / A conversion of the fine adjustment output system with the calibration data for correcting the output error voltage of the D / A converter of the coarse adjustment output system as digital data corresponding to the theoretical value of the D / A converter of the coarse adjustment output system A data correction unit written to be digital data input to the device,
An arbitrary waveform generator comprising: an adder for adding and outputting an output voltage of a D / A converter of a coarse adjustment output system and an output voltage of a D / A converter of a fine adjustment output system.   2. The arbitrary waveform generator according to claim 1, wherein an amplification factor of the fine adjustment output system of the adder is set smaller than an amplification factor of the coarse adjustment output system. In semiconductor test equipment where the output of the arbitrary waveform generator is applied to the DUT via the test head and performance board,
The arbitrary waveform generator is
A coarse adjustment output system and a fine adjustment output system D / A converter having the same characteristics and driven by a common clock;
Timing adjustment means for delaying digital data input to the D / A converter of the coarse adjustment output system by one clock;
The D / A conversion of the fine adjustment output system is based on the assumption that the calibration data for correcting the output error voltage of the D / A converter of the coarse adjustment output system is the digital data corresponding to the theoretical value of the D / A converter of the coarse adjustment output system. A data correction unit written to be digital data input to the device,
A semiconductor test apparatus comprising: an adder for adding and outputting an output voltage of a D / A converter of a coarse adjustment output system and an output voltage of a D / A converter of a fine adjustment output system.   4. The semiconductor test apparatus according to claim 3, wherein an amplification factor of the fine adjustment output system of the adder of the arbitrary waveform generator is set smaller than an amplification factor of the coarse adjustment output system.   5. The semiconductor test apparatus according to claim 3, wherein the arbitrary waveform generator performs calibration including an error voltage at an arbitrary connection point from the arbitrary waveform generator to an input terminal of the DUT.

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