JP2000228373A - Manufacture of electrode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain an electrode that it is hard to be oxidized, if heated in the oxygen atmosphere and the electrical characteristics are not deteriorated by a method, wherein there is formed an electrode structure in which an electrode material other than a barrier metal material and the barrier metal material are embedded in a contact hole as a laminated structure. SOLUTION: This manufacturing method of an electrode includes the sequential steps of a step of forming an insulated film on a semiconductor substrate for flattening, a step of forming a contact hole 4 in an insulated film, a step of forming a first barrier metal 7Ir in the bottom part and the sidewall of the contact hole, a step of embedding the contact hole with a conductive material, a step of removing the conductive material by etchbacking to a desired thickness, and a step of embedding the contact hole with a second barrier metal. As a result, it is possible to attain an electrode structure, in which the conductive material other than a barrier metal material and the barrier metal material are embedded in the contact hole as a laminated structure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an electrode used in an LSI.

[0002]

[Prior Art] Reference: T. Kachi, K. Shoji, H. Yamashita,
T.Kisu, K.Torii, T.Kumihashi, Y.Fujisaki, and N.Yok
oyama, Proceedings of Symp.VLSI Tech., 1998, pp
126-127A Scalable Single-transistor / single-capac
itor Memory Cell Structure Characterized by an Ang
led-capacitor Layout for Megabit FeRAMs 1T-1C (1 transistor-1 capacitor)
It is disclosed that a cell size of 4.5 μm ² was realized with a 0.5 μm rule for a ferroelectric memory (FeRAM) of the type. The structure of the cell is a stack type, and the arrangement of the cell is devised.

A ferroelectric capacitor is Pt (50 nm) / PZT (150 n
m) / Pt (200 nm) / TiN (50 nm). The formation method is a dry etching method in which no residue remains on the pattern side wall of the laminated structure. This ferroelectric capacitor is connected to a lower MOS transistor by a polysilicon plug to constitute a 1T-1C type ferroelectric memory.

[0004]

In the above-mentioned conventional technique, the polysilicon plug is not oxidized by the heat treatment in the oxygen atmosphere at the time of firing the PZT, which is a ferroelectric film, so that electrical contact failure does not occur. As described above, a thick laminated film Pt (200 nm) / TiN (50 nm) is adopted as the lower electrode.

The pattern side wall of the ferroelectric capacitor processed by dry etching has a shape that is greatly inclined with respect to the substrate. The result is a ferroelectric capacitor
The stacked structure of Pt (50 nm) / PZT (150 nm) / Pt (200 nm) / TiN (50 nm) has a trapezoidal shape.

For this reason, there is a problem that the lower electrode having a large film thickness causes the overhang of the pattern side wall (near the bottom of the trapezoid described above) to be increased, and it is difficult to increase the degree of integration.

[0007]

A process for forming an insulating film on a semiconductor substrate and planarizing the same, a process for forming a contact hole in the insulating film, and forming a first barrier metal on the bottom and side walls of the contact hole. And a step of filling the contact hole with a conductive material, a step of removing the conductive material by a desired thickness by etch back, and a step of filling the contact hole with a second barrier metal. As a result, an electrode structure in which a conductive material other than the barrier metal material and a barrier metal material are embedded in the contact hole in a laminated structure is obtained.

Further, even if this electrode is heat-treated in an oxygen atmosphere, it is hardly oxidized and the electric characteristics are not deteriorated. Therefore,
Even when the ferroelectric capacitor is laminated on the electrode formed according to the present invention, it is not necessary to increase the thickness of the electrode of the capacitor (especially, the lower electrode), and the protrusion of the side wall of the ferroelectric capacitor can be reduced. Therefore, the above problem can be eliminated.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention describes a method of manufacturing an electrode suitable for increasing the degree of integration. In the embodiment of the present invention, the electrode of the capacitor will be described, but the present invention is not limited to this. The present capacitance element is assumed to be used together with a control element such as a MOS transistor as a circuit configuration. Further, the structure of the element is called a stack structure, and connection with a control element below the present capacitive element is performed on the lower surface of the lower electrode of the present capacitive element.

The electrode of the present invention comprises a plug made of tungsten and a barrier metal formed on the plug. The barrier metal suppresses diffusion of oxygen and prevents oxidation of tungsten. Then, a capacitive element is arranged above the barrier metal. The capacitance element has a dielectric material disposed between a lower electrode and an upper electrode. The capacitive element in the present embodiment uses IrO _{2 for} the material of the lower electrode and the upper electrode, and an example in which SrBi ₂ Ta ₂ O ₉ (SBT), which is a ferroelectric, is used for the dielectric material. It is not limited.

<Example> An example of the present invention will be described below with reference to the drawings. Here, a description will be given from the step before the formation of the capacitive element, in which an interlayer insulating film is formed after the MOS transistor is formed, and a flattening process is performed to reduce surface unevenness.

First, as shown in FIG. 1A, a contact hole is formed in a desired portion of an interlayer insulating film (3) which has been planarized in advance by known photolithography and dry etching.
Open (4) to expose, for example, the source or drain region (2) of the MOS transistor.

Next, as shown in FIG. 1 (b), using a target made of Ti, 0.05
Then, TiN (5) is formed on the entire surface of the substrate at 750 ° C. for 30 seconds by performing a nitriding treatment (RTN) by a rapid heating method in N ₂ . At this time, TiN (5) is also formed on the bottom and side walls of the contact hole (4).

Next, as shown in FIG. 1C, tungsten (W) is formed on the entire surface of the substrate by a known CVD method, and the contact hole (4) is filled with W (6). At this time, W (6) is also formed on the interlayer insulating film (3) via the TiN (5).

Next, as shown in FIG. 2 (d), using a slurry using a hydrogen peroxide solution as a base, a pad having relatively high hardness as a polishing pad, for example, IC14 manufactured by Rodale Nitta Co., Ltd.
Chemical mechanical polishing using CMP (CMP: chemical mechanica
l polishing and W and TiN other than contact hole (4)
Is removed and flattened.

Next, as shown in FIG. 2E, W (6) is dry-etched, and W (6) in the contact hole (4) is etched back to a depth of, for example, 0.2 μm.

Next, as shown in FIG. 2 (f), Ir (7) used as a barrier metal is deposited on the entire surface of the substrate by sputtering.
Deposit 0.2um. At this time, the contact hole may be filled with Ir (7) with a thickness substantially equal to or greater than the depth of the etched back W (6). That is, the contact hole does not necessarily need to be completely filled with Ir (7), and the thickness of 0.2 μm of Ir (7) is only an example.

Next, as shown in FIG. 3 (g), the contact hole is formed by a CMP using a pad having relatively low hardness as a polishing pad, for example, Suba400 manufactured by Rodale Nitta while dropping pure water without using a slurry. Remove Ir except 4). this
Ir removal is performed by using SiO ₂ which is a constituent material of Ir and the interlayer insulating film (3).
This is because Ir and W are easily peeled off due to poor adhesion, and that Ir and W are easily alloyed and therefore have high adhesion.

Next, as shown in FIG. 3 (h), after scrub cleaning is performed to remove particles, a relatively hard pad such as Rodale Nitta is used as a polishing pad using a slurry based on ammonia. The surface of the exposed oxide film is polished by CMP using IC1400, and the scratches formed in the previous step and the irregularities on the Ir (7) surface are removed.

Next, as shown in FIG. 3I, a laminated structure IrO ₂ / SBT / IrO ₂ of the capacitive element is formed. In this embodiment, Sol-Gel
In order to form the SBT film (8) by the (sol-gel) method, for example, heat treatment at 450 ° C. for 1 hour in an oxygen atmosphere
In addition, heat treatment, for example, at 750 ° C. for one hour in an oxygen atmosphere is required as the main firing. At this time, the lower electrode IrO ₂
Although oxygen diffuses through (9), the W plug (6) is not oxidized because Ir (7) is formed as a barrier metal. Therefore, even when a ferroelectric capacitor is laminated on the upper layer,
It is not necessary to increase the thickness of the lower electrode of the capacitor. Therefore, it is possible to realize an electrode structure suitable for high integration, in which the lower electrode of the capacitor has little overhang in the lateral direction.

In this embodiment, an example using Ir as a barrier metal is described, but an alloy containing Ir or a compound containing Ir can be used in the same manner. In addition, as can be seen from the description of the prior art, Pt may be used as a diffusion barrier for oxygen, but it is known that Pt also has poor adhesion to SiO ₂ and easily peels off. Method and structure P
Obviously, it can be realized by an alloy containing t or Pt, or a compound containing Pt.

The electrode of this embodiment is used for processing a barrier metal.
Since the damascene process using CMP is used, the shape of the barrier metal is determined by the shape of the contact hole opened in the insulating film. Further, fine processing is possible even with a barrier metal material that is difficult to dry-etch.

[0023]

As described above in detail with reference to the embodiments, in the electrode structure of the present invention, an electrode structure in which an electrode material other than a barrier metal material and a barrier metal material are embedded in a contact hole in a laminated structure is formed. It becomes possible to do.

Further, even if the electrode structure manufactured according to the present invention is heat-treated in an oxygen atmosphere, the electrode is hardly oxidized and the electric characteristics are not deteriorated. Therefore, even when, for example, a ferroelectric capacitor is laminated on the electrode structure formed according to the present invention, it is not necessary to increase the thickness of the capacitor electrode (particularly, the lower electrode), and it is possible to reduce the protrusion of the pattern side wall. And the degree of integration can be increased.

Furthermore, even with a barrier metal material that is difficult to dry-etch, the pattern edge can be made substantially perpendicular to the substrate, so that a structure suitable for miniaturization can be realized.

Thus, a stacked ferroelectric capacitor for FeRAM or a capacitor for DRAM requiring high-temperature treatment in oxygen can be realized without deteriorating the characteristics of the electrodes.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram (1) of an embodiment of the present invention.

FIG. 2 is an embodiment (2) of the present invention following FIG. 1;

FIG. 3 is an embodiment (3) of the present invention following FIG. 2;

[Explanation of symbols]

(1) Gate (2) Source / drain region (3) Interlayer insulating film (4) Contact hole (5) TiN (6) W (7) Ir (8) SBT (9) (10) IrO ₂

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/8242 H01L 29/78 371 21/8247 29/788 29/792 F term (Reference) 4M104 BB30 CC01 DD08 DD37 DD43 DD65 DD75 DD80 DD86 FF17 FF18 FF22 GG09 GG16 HH14 HH20 5F001 AA17 AB02 AD04 AD33 AF06 AG29 AG30 5F038 AC09 AC15 CD18 DF05 EZ01 EZ11 5F083 BS25 BS48 FR02 GA09 JA17 JA38 JA39 JA40 PR43 PR05 PR06

Claims (6)

[Claims] 1. A step of forming an insulating film on a semiconductor substrate for planarization, a step of forming a contact hole in the insulating film, and a step of forming a first barrier metal on a bottom and a side wall of the contact hole. Sequentially embedding the contact hole with a conductive material, removing the conductive material by a desired thickness by etch back, and embedding the contact hole with a second barrier metal. A method for producing an electrode, comprising: 2. A step of forming a field effect transistor on a semiconductor substrate, a step of forming an interlayer insulating film on the semiconductor substrate to planarize the field effect transistor, and forming a contact hole in the interlayer insulating film to form the field effect transistor. Exposing one of the source and the drain of the contact hole, forming a first barrier metal on the entire surface of the semiconductor, and attaching the first barrier metal to the side wall and the bottom of the contact hole and the interlayer insulating film; Depositing a conductive material to completely fill the contact hole, removing the first barrier metal and the conductive material except for the inside of the contact hole by a chemical mechanical polishing method, and etching back by etching back. Removing the conductive material in a contact hole by a desired thickness, and etching back the entire surface of the semiconductor substrate. Forming a second barrier metal with a thickness substantially equal to or greater than the thickness of the conductive material removed; and excluding the inside of the contact hole, the second barrier metal is formed by the chemical mechanical polishing method. And a step of sequentially removing the same. 3. The method for manufacturing an electrode according to claim 1, wherein the first barrier metal is TiN. 4. The method for manufacturing an electrode according to claim 1, wherein the second barrier metal is Ir, an alloy with Ir,
Alternatively, a method for producing an electrode, which is a compound with Ir. 5. The method for manufacturing an electrode according to claim 1, wherein the second barrier metal is Pt, an alloy with Pt,
Alternatively, a method for producing an electrode, which is a compound with Pt. 6. The method for manufacturing an electrode according to claim 1, wherein the conductive material is W.