CN213071121U

CN213071121U - Fan-out type packaging structure

Info

Publication number: CN213071121U
Application number: CN202022013524.8U
Authority: CN
Inventors: 陈彦亨; 林正忠
Original assignee: SJ Semiconductor Jiangyin Corp
Current assignee: SJ Semiconductor Jiangyin Corp
Priority date: 2020-09-15
Filing date: 2020-09-15
Publication date: 2021-04-27
Anticipated expiration: 2030-09-15

Abstract

The utility model provides a fan-out type packaging structure, fan-out type packaging structure include rewiring layer, passivation layer, semiconductor chip, encapsulated layer, recess, first metal lug, second metal lug, keysets, pile up the chip package body, passive component and filling layer. The utility model integrates a plurality of chips with different functions into one packaging structure, thereby improving the integration of the fan-out type packaging structure; through the rewiring layer, the adapter plate and the metal bumps, three-dimensional vertical stacking packaging is realized, the integration level of a packaging structure can be effectively improved, and a conducting path can be effectively shortened, so that the power consumption is reduced, the transmission speed is improved, and the data processing capacity is increased.

Description

Fan-out type packaging structure

Technical Field

The utility model relates to a semiconductor package technical field especially relates to a fan-out type packaging structure.

Background

Lower cost, more reliable, faster, and higher density circuits are sought after goals for integrated circuit packaging. With the arrival of the 5G communication and artificial intelligence era, the data volume to be transmitted and processed by high-speed interaction of chips applied to the related fields is large, the requirements on the mobile internet and the internet of things are more and more strong, and the miniaturization and the multi-functionalization of electronic terminal products become a great trend of industrial development. How to integrate and package different kinds of high-density chips together to form a system with powerful functions and small volume power consumption has become a great challenge in the field of advanced packaging of semiconductor chips.

Among them, the fan-out wafer level package (FOWLP) has become one of the more advanced fan-out packaging methods due to its more input/output ports (I/O) and better integration flexibility. However, in the conventional fan-out package technology, the area of the package is large and the thickness of the package is high due to limited wiring precision, and the problems of multiple processes, low reliability and the like exist.

Therefore, it is necessary to provide a new fan-out package structure.

SUMMERY OF THE UTILITY MODEL

In view of the above shortcomings in the prior art, an object of the present invention is to provide a fan-out package structure for solving the problems in the prior art that the package size is difficult to shrink and the package integration level is low.

To achieve the above and other related objects, the present invention provides a fan-out package structure, comprising:

a rewiring layer including opposing first and second faces;

a passivation layer including opposing first and second faces;

the semiconductor chip is positioned between the second surface of the passivation layer and the first surface of the rewiring layer, the back surface of the semiconductor chip is bonded with the second surface of the passivation layer, and the front surface of the semiconductor chip is far away from the passivation layer and is electrically connected with the rewiring layer;

the packaging layer is positioned between the second surface of the passivation layer and the first surface of the rewiring layer and covers the passivation layer, the rewiring layer and the semiconductor chip;

the groove penetrates through the passivation layer and the packaging layer to expose the metal wiring layer in the rewiring layer;

a first metal bump on a second surface of the rewiring layer and electrically connected to the rewiring layer;

the second metal bump is positioned in the groove and is electrically connected with the rewiring layer;

the adapter plate is positioned on the first surface of the passivation layer and is electrically connected with the second metal bump;

the stacked chip packaging body and the passive element are positioned on the adapter plate and are electrically connected with the adapter plate;

and the filling layer is positioned between the stacked chip packaging body and the adapter plate and is used for filling a gap between the stacked chip packaging body and the adapter plate.

Optionally, the package structure further comprises a molding layer covering the interposer, the stacked chip package and the passive component.

Optionally, the height of the second metal bump is greater than the height of the semiconductor chip.

Optionally, the stacked chip package includes an ePoP memory.

Optionally, the passive element includes one or a combination of a resistor, a capacitor, and an inductor.

Optionally, the encapsulation layer includes one of an epoxy layer, a polyimide layer, and a silicone layer.

Optionally, the filling layer includes one of an epoxy layer, a polyimide layer, and a silicone layer.

As described above, the fan-out package structure of the present invention can integrate a plurality of chips with different functions into one package structure, thereby improving the integration of the fan-out package structure; through the rewiring layer, the adapter plate and the metal bumps, three-dimensional vertical stacking packaging is realized, the integration level of a packaging structure can be effectively improved, and a conducting path can be effectively shortened, so that the power consumption is reduced, the transmission speed is improved, and the data processing capacity is increased.

Drawings

Fig. 1 shows a flow chart of a manufacturing process of the fan-out package structure of the present invention.

Fig. 2 to fig. 18 show the schematic structural diagrams of the fan-out package structure in the manufacturing process of the present invention, wherein fig. 16 and fig. 18 show the schematic structural diagrams of two different fan-out package structures of the present invention.

Description of the element reference numerals

100 support substrate

200 separating layer

300 passivation layer

400 semiconductor chip

500 encapsulation layer

600 rewiring layer

601 dielectric layer

602 metal wiring layer

700 first metal bump

800 supporting body

900 groove

110 second metal bump

120 adapter plate

130 stacked chip package

140 passive element

150 filling layer

160 plastic packaging layer

Detailed Description

The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structure are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, amount and ratio of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.

As shown in fig. 1, the present embodiment provides a fan-out package method, which can integrate a plurality of chips with different functions into one package structure, thereby improving the integrity of the fan-out package structure; through the rewiring layer, the adapter plate and the metal bumps, three-dimensional vertical stacking packaging is realized, the integration level of a packaging structure can be effectively improved, and a conducting path can be effectively shortened, so that the power consumption is reduced, the transmission speed is improved, and the data processing capacity is increased.

First, referring to fig. 2, a supporting substrate 100 is provided, and a separation layer 200 is formed on the supporting substrate 100.

Specifically, the support substrate 100 may include one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate. In the present embodiment, the supporting substrate 100 is preferably a glass substrate which has low cost, is easy to form the separation layer 200 on the surface thereof, and can reduce the difficulty of the subsequent peeling process, but is not limited thereto. The separation layer 200 may include one of an adhesive tape and a polymer layer, and when the polymer layer is used, a polymer may be applied to the surface of the support substrate 100 by a spin coating process and then cured by a uv curing or thermal curing process. In this embodiment, the separation layer 200 is an LTHC light-to-heat conversion layer, so that the LTHC light-to-heat conversion layer may be heated based on laser and other methods in the subsequent steps, so that the supporting substrate 100 is separated from the LTHC light-to-heat conversion layer, thereby reducing the difficulty of the stripping process and reducing the damage.

Next, referring to fig. 3 to 4, a passivation layer 300 is formed on the separation layer 200, wherein the passivation layer 300 includes a first surface contacting the separation layer 200 and an opposite second surface.

Specifically, the passivation layer 300 may include one of epoxy, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the formation and material of the passivation layer 300 are not limited herein.

Next, referring to fig. 4, a semiconductor chip 400 is provided, wherein the semiconductor chip 400 is located on the second side of the passivation layer 300, the back side of the semiconductor chip 400 is bonded to the passivation layer 300, and the front side of the semiconductor chip 400 is far away from the second side of the passivation layer 300.

Next, referring to fig. 5 to 6, the passivation layer 300 and the semiconductor chip 400 are packaged by a packaging layer 500, and the bonding pads of the semiconductor chip 500 are exposed by the packaging layer 500.

Specifically, the method for forming the encapsulation layer 500 may include one of compression molding, transfer molding, liquid encapsulation molding, vacuum lamination and spin coating, and the material of the encapsulation layer 500 may include one of polyimide, silicone and epoxy resin. After the encapsulation layer 500 is formed, a grinding or polishing method may be further included to act on the top surface of the encapsulation layer 500 to provide a flat top surface of the encapsulation layer 500.

Next, referring to fig. 7, a redistribution layer 600 is formed on the encapsulation layer 500, the redistribution layer 600 includes a first surface contacting the encapsulation layer 500 and an opposite second surface, and the redistribution layer 600 is electrically connected to the pads of the semiconductor chip 400.

Specifically, the redistribution layer 600 includes a dielectric layer 601 and a metal wiring layer 602, and the dielectric layer 601 and the metal wiring layer 602 may be repeatedly formed according to process requirements, so as to increase conductive paths. The dielectric layer 601 may be made of one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass; the material of the metal wiring layer 602 may include one of copper, aluminum, nickel, gold, silver, and titanium.

Next, referring to fig. 8, a first metal bump 700 is formed on the second surface of the redistribution layer 600, and the first metal bump 700 is electrically connected to the redistribution layer 600. The first metal bump 700 may include one of a copper metal bump, a nickel metal bump, a tin metal bump, and a silver metal bump, and the specific kind may be selected as required.

Next, referring to fig. 9, a carrier 800 is provided, and the supporting substrate 100 is peeled off to expose the first side of the passivation layer 300.

Next, referring to fig. 10, the passivation layer 300 and the encapsulation layer 500 are laser etched to form a groove 900, and the groove 900 exposes the metal wiring layer 602 in the redistribution layer 600.

Next, referring to fig. 11, a second metal bump 110 is formed in the groove 900, and the second metal bump 110 is electrically connected to the redistribution layer 600.

Specifically, the second metal bump 110 may include one of a copper metal bump, a nickel metal bump, a tin metal bump, and a silver metal bump, and the specific kind may be selected according to the requirement.

As an example, the height of the second metal bump 110 is greater than the height of the semiconductor chip 400, so as to facilitate the subsequent electrical connection between the interposer 120 and the second metal bump 110.

Next, referring to fig. 12, the interposer 120 is provided, the interposer 120 is located on the first surface of the passivation layer 300, and the interposer 120 is electrically connected to the second metal bump 110.

Next, referring to fig. 13 to 14, a stacked chip package 130 and a passive component 140 are provided, the stacked chip package 130 and the passive component 140 are located on the interposer 120, and both the stacked chip package 130 and the passive component 140 are electrically connected to the interposer 120.

As an example, the stacked chip package 130 includes an ePoP memory.

As an example, the passive element 140 includes one or a combination of a resistor, a capacitor, and an inductor.

Specifically, in the present embodiment, the stacked chip package 130 is an ePoP memory, but the present invention is not limited thereto, and other packages may be adopted according to the need, and similarly, the passive component 140 may also be disposed according to the need, and is not limited herein.

Next, referring to fig. 15, a filling layer 150 is used to fill a gap between the stacked chip package 130 and the interposer 120.

Specifically, the filling layer 150 may include one of an epoxy layer, a polyimide layer and a silicone layer, so as to fill the gap with the insulating filling layer 150, so as to enhance the bonding effect between the stacked chip package 130 and the interposer 120, thereby forming a protective layer. The material of the filling layer 150 is not limited herein.

Finally, referring to fig. 16, dicing is performed to form a fan-out package structure.

As an example, after the filling layer 150 is formed and before the dicing, a step of encapsulating the interposer 120, the stacked chip package 130 and the passive component 140 with a molding compound layer 160 is further included.

Specifically, referring to fig. 17 and 18, the molding layer 160 includes one of an epoxy layer, a polyimide layer, and a silicone layer, and the specific preparation method may refer to the encapsulation layer 500, which is not described herein again.

Referring to fig. 16, the present embodiment further provides a fan-out package structure, which can be prepared by the above-mentioned preparation method, but is not limited thereto. In this embodiment, the fan-out package structure is prepared by the above preparation method, and therefore, details regarding the selection of the preparation method, the material, and the like of the fan-out package structure are not described herein.

Specifically, the fan-out package structure includes a redistribution layer 600, a passivation layer 300, a semiconductor chip 400, a package layer 500, a groove 900, a first metal bump 700, a second metal bump 110, an interposer 120, a stacked chip package 130, a passive component 140, and a filling layer 150.

Wherein the redistribution layer 600 includes a first side and a second side opposite to each other; the passivation layer 300 includes a first side and a second side opposite to each other; the semiconductor chip 400 is located between the second surface of the passivation layer 300 and the first surface of the redistribution layer 600, the back surface of the semiconductor chip 400 is bonded to the second surface of the passivation layer 300, and the front surface of the semiconductor chip 400 is away from the passivation layer 300 and is electrically connected to the redistribution layer 600; the encapsulation layer 500 is located between the second surface of the passivation layer 300 and the first surface of the redistribution layer 600, and covers the passivation layer 300, the redistribution layer 600 and the semiconductor chip 400; the groove 900 penetrates through the passivation layer 300 and the encapsulation layer 500 to expose the metal wiring layer 602 in the redistribution layer 600; the first metal bump 700 is located on a second side of the redistribution layer 600 and electrically connected to the redistribution layer 600; the second metal bump 110 is located in the groove 900 and electrically connected to the redistribution layer 600; the interposer 120 is located on the first surface of the passivation layer 300 and electrically connected to the second metal bump 110; the stacked chip package 130 and the passive component 140 are located on the interposer 120 and electrically connected to the interposer 120; the filling layer 150 is located between the stacked chip package 130 and the interposer 120, and fills a gap between the stacked chip package 130 and the interposer 120.

As an example, a molding layer 160 covering the interposer 120, the stacked chip package 130 and the passive component 140 is further included.

As an example, the height of the second metal bump 110 is greater than the height of the semiconductor chip 400.

As an example, the stacked chip package 130 includes an ePoP memory.

As an example, the encapsulation layer 500 includes one of an epoxy layer, a polyimide layer, and a silicone layer.

As an example, the filling layer 150 includes one of an epoxy layer, a polyimide layer, and a silicone layer.

In summary, the fan-out package structure of the present invention can integrate a plurality of chips with different functions into one package structure, thereby improving the integration of the fan-out package structure; through the rewiring layer, the adapter plate and the metal bumps, three-dimensional vertical stacking packaging is realized, the integration level of a packaging structure can be effectively improved, and a conducting path can be effectively shortened, so that the power consumption is reduced, the transmission speed is improved, and the data processing capacity is increased.

The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A fan-out package structure, comprising:

a rewiring layer including opposing first and second faces;

a passivation layer including opposing first and second faces;

a second metal bump in the groove and electrically connected to the rewiring layer, the second metal bump protruding from the passivation layer;

the adapter plate is positioned on the first surface of the passivation layer and is electrically connected with the second metal bump, and a gap is formed between the adapter plate and the passivation layer;

a filling layer located between the stacked chip packages and the interposer and filling up a gap between the stacked chip packages and the interposer;

the package structure further comprises a plastic package layer covering the adapter plate, the stacked chip packages and the passive element.

2. The fan-out package structure of claim 1, wherein: the stacked chip package includes an ePoP memory.

3. The fan-out package structure of claim 1, wherein: the passive element comprises one or a combination of a resistor, a capacitor and an inductor.

4. The fan-out package structure of claim 1, wherein: the packaging layer comprises one of an epoxy resin layer, a polyimide layer and a silica gel layer.

5. The fan-out package structure of claim 1, wherein: the filling layer comprises one of an epoxy resin layer, a polyimide layer and a silica gel layer.