CN117973282B - Chip time sequence risk prediction method, electronic equipment and medium - Google Patents
Chip time sequence risk prediction method, electronic equipment and medium Download PDFInfo
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Abstract
The invention relates to the technical field of chips, in particular to a chip time sequence risk prediction method, electronic equipment and medium, wherein the method comprises the following steps of S1, selecting a reference unit, and determining a normalized logic level threshold value R based on the reference unit; step S2, obtaining all to-be-processed time sequence paths { A 1,A2,…,An,…,AN } in the to-be-processed gate-level netlist; step S3, obtaining a normalized logic level number B i n of each a i n relative to the reference unit, and obtaining a total normalized logic level number C i n corresponding to a n based on B i n: step S4, comparing each C i n with the logic level number threshold R, and determining A n with C i n larger than the logic level number threshold R as the time sequence risk time sequence path. The method can realize accurate chip time sequence risk prediction based on the gate-level netlist generated by logic synthesis, and improves chip development efficiency.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a method for predicting chip timing risk, an electronic device, and a medium.
Background
Chip designs typically include multiple timing paths that include multiple levels of standard cells connected in series. When data is transmitted through the timing path, each level of standard cells in the timing path needs to be traversed. The longer the timing path, the greater the impact on the timing, which may result in lower operating frequencies and poorer performance of the timing path. The prior logic synthesis tool generates a netlist only to obtain the level number of standard cells in a time sequence path, but the standard cells have different structures and different sizes, so the time sequence risk cannot be predicted directly through the level number of the standard cells in the time sequence path. The prediction can only be performed after the layout is generated in the physical layout and wiring stage, but a great amount of work is required to be performed from the gate level netlist generated by logic synthesis to the physical layout and wiring layout, when the chip time sequence risk is predicted, the chip code is required to be returned to be modified again, the logic synthesis is performed again, and if the chip time sequence is predicted again after the layout is generated, the chip development efficiency is reduced. Therefore, how to accurately predict the chip timing risk at an earlier stage and improve the chip development efficiency is a technical problem to be solved.
Disclosure of Invention
The invention aims to provide a chip time sequence risk prediction method, electronic equipment and medium, which can realize accurate chip time sequence risk prediction based on a gate-level netlist generated by logic synthesis and improve chip development efficiency.
According to a first aspect of the present invention, there is provided a method for predicting chip timing risk, including:
S1, selecting a reference unit, and determining a normalized logic level threshold R based on the reference unit;
Step S2, obtaining all to-be-processed time sequence paths { A 1,A2,…,An,…,AN } in a to-be-processed gate-level netlist, wherein the to-be-processed gate-level netlist is generated by logic synthesis based on chip design codes, A n is an N-th to-be-processed time sequence path, N is a range of values from 1 to N, N is an i-th standard unit corresponding to A n in total number ,An={A1 n,A2 n,...,Ai n,...Af(n) n},Ai n of to-be-processed time sequence paths in the gate-level netlist, i is a range of values from 1 to f (N), and f (N) is a standard unit series corresponding to A n;
Step S3, obtaining a normalized logic level number B i n of each a i n relative to the reference unit, and obtaining a total normalized logic level number C i n corresponding to a n based on B i n:
；
Step S4, comparing each C i n with the logic level number threshold R, and determining A n with C i n larger than the logic level number threshold R as the time sequence risk time sequence path.
According to a second aspect of the present invention, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method according to the first aspect of the invention.
According to a third aspect of the present invention there is provided a computer readable storage medium storing computer executable instructions for performing the method of the first aspect of the present invention.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the chip time sequence risk prediction method, the electronic equipment and the medium provided by the invention can achieve quite technical progress and practicality, have wide industrial utilization value, and have at least the following beneficial effects:
The method comprises the steps of selecting a reference unit, determining a logic level threshold based on the reference unit, normalizing all time sequence paths to be processed based on the reference unit, normalizing the total normalized logic level of the time sequence paths to be processed, and predicting the time sequence risk time sequence paths based on the total normalized logic level of the time sequence paths to be processed and the logic level threshold. The method can realize accurate chip time sequence risk prediction based on the gate-level netlist generated by logic synthesis, and improves chip development efficiency.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a method for predicting chip timing risk according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The embodiment of the invention provides a method for predicting chip time sequence risk, which is shown in fig. 1 and comprises the following steps:
And S1, selecting a reference unit, and determining a normalized logic level threshold R based on the reference unit.
It should be noted that the normalized logic level threshold R is related to the target frequency of the chip design. The reference unit is the basis for subsequent normalization processing, the total normalized logic level number obtained after normalization processing of all the time sequence paths (TIMING PATH) to be processed cannot exceed the logic level number threshold, if so, the time sequence is not in accordance with the requirement, and the running frequency of the time sequence paths to be processed cannot reach the target frequency, so that the chip performance is affected. The existing logic synthesis tool can only acquire the standard cell series corresponding to the time sequence path to be processed, but the standard cell series cannot accurately predict the chip time sequence risk. According to the embodiment of the invention, the standard units are selected, and normalization processing is carried out on all the standard units based on the standard units, so that the total normalized logic progression corresponding to the time sequence path to be processed is obtained, and the chip time sequence risk prediction can be more accurately carried out based on the total normalized progression and the logic progression threshold value.
Note that the timing paths to be processed are of various types, and specifically may include REG2REG type, REG2RAM type, IN2REG type, REG2OUT type, and the like. The REG2REG type, REG2RAM type, IN2REG type and REG2OUT type are common structures IN chip design and are not described IN detail herein. It should be noted that, for different types of timing paths, the corresponding normalized logic level thresholds may be different, and if the timing path to be processed is only one type of timing path, the normalized logic level threshold R corresponding to the one type may be directly obtained. If the timing path includes multiple types, a normalized logic level threshold R corresponding to each of the multiple types needs to be obtained, and when the total normalized logic level corresponding to the subsequent a n is compared with R, the normalized logic level threshold R corresponding to the type of the timing path needs to be compared.
Step S2, all the time sequence paths { A 1,A2,…,An,…,AN } to be processed in the gate-level netlist to be processed are obtained, the gate-level netlist to be processed is generated by logic synthesis based on chip design codes, wherein A n is the N-th time sequence path to be processed, the value range of N is 1 to N, N is the i-th standard unit corresponding to A n in the total number ,An={A1 n,A2 n,...,Ai n,...Af(n) n},Ai n of the time sequence paths to be processed in the gate-level netlist, the value range of i is 1 to f (N), and f (N) is the standard unit series corresponding to A n.
The timing path to be processed may be set at a plurality of positions corresponding to the chip design, for example, may be set between two triggers, and the sending trigger transmits data to the receiving trigger through the timing path to be processed. The gate-level netlist to be processed can be directly generated through logic synthesis by inputting chip design codes into an existing logic synthesis tool, and details are not repeated here. The chip design may be specifically a chip such as GPU.
Step S3, obtaining a normalized logic level number B i n of each a i n relative to the reference unit, and obtaining a total normalized logic level number C i n corresponding to a n based on B i n:
。
It should be noted that, because different standard cell structures may be different, and sizes of standard cells with the same structure may also be different, so that the number of stages of the standard cells cannot accurately reflect the time sequence risk.
Step S4, comparing each C i n with the logic level number threshold R, and determining A n with C i n larger than the logic level number threshold R as the time sequence risk time sequence path.
In step S4, if the timing path to be processed is only one type of timing path, C i n is directly compared with the normalized logic level threshold R corresponding to the type. If multiple types of timing paths are included, C i n needs to compare to the normalized logic level number threshold R of the timing path type corresponding to A n. As an embodiment, the step S1 includes:
Step S11, selecting a reference unit, and acquiring delay time t corresponding to transmission data of the reference unit.
It should be noted that the reference unit may be any standard unit, any component, or a specific value, for example, 1 ohm. As a preferred embodiment, the standard unit with the highest frequency of occurrence in the chip design can be selected as the reference unit, or the component with the highest frequency of occurrence in the chip design can be selected as the reference unit, and the two settings can further improve the accuracy of normalization processing, thereby improving the accuracy of chip time sequence prediction. Specifically, a two-input inverter may be selected as the reference cell.
The delay time corresponding to the reference unit can be obtained by carrying out statistical analysis on data obtained by time sequence analysis carried out in the historical film streaming stage.
Step S12, a target frequency F and a target frequency allowance F are obtained.
The target frequency is a frequency to be achieved by the chip design, but a certain target frequency margin is usually set as long as the frequency of the chip operation reaches (target frequency-target frequency margin).
Step S13, determining a normalized logic level threshold R based on the delay time t, the target frequency F and the target frequency margin F:
R=（F-f）/t。
It should be noted that, in one to-be-processed timing path, if all the to-be-processed timing paths are set as reference units, at most, only R-level reference units can be set under the condition that the operating frequency requirement of the chip is met, and if the operating frequency of the chip is higher than R-level reference units, the operating frequency of the chip cannot meet the requirement. The f-values of the different timing paths may be different and, therefore, the corresponding normalized logic level thresholds R may also be different. If the timing path to be processed relates to multiple timing path types, a normalized logic level number threshold value R corresponding to each timing path type needs to be obtained, and when the normalized logic level number threshold value R is compared with the normalized logic level number threshold value R, the normalized logic level number threshold value R of the corresponding type needs to be classified and compared.
In order to accurately determine whether each time sequence path to be processed can meet the requirement (target frequency-target frequency margin), it is necessary to perform normalization processing on each standard cell in the time sequence path to be processed with respect to the reference cell to obtain a normalized logic level number of each standard cell in the time sequence path to be processed with respect to the reference cell, and in step S3, a normalized logic level number B i n of each a i n with respect to the reference cell is obtained, including:
step S31, obtaining a standard cell library { D 1,D2,...,Dm,...,DM},Dm corresponding to the chip design as an mth standard cell in the standard cell library corresponding to the chip design, wherein the value range of M is 1 to M, and M is the total number of standard cells in the standard cell library corresponding to the chip design.
It should be noted that, in order to facilitate calculation of the normalized logic level, the normalized logic level corresponding to each standard cell in the standard cell library may be obtained in advance. The standard cell library can be standard cell libraries of different processes, specifically set according to the chip design requirement, for example, can be standard cell libraries of ultra-deep submicron processes.
Step S32, a transistor resistance network model E m corresponding to each standard cell D m is established according to the equivalent resistance from the source to the drain of each standard cell D m, a transistor resistance network model corresponding to the reference cell is established according to the equivalent resistance from the source to the drain of the reference cell, and an equivalent resistance F m corresponding to E m and an equivalent resistance G of the transistor resistance network model corresponding to the reference cell are obtained.
It should be noted that, according to different factors such as standard cell size and structure, when the standard cell is set, operations such as transistor folding are performed, so that different standard cells may have different equivalent resistance structures, and therefore, corresponding equivalent resistance values may be obtained by building transistor resistance network models for the standard cell and the reference cell. The existing method for establishing the transistor resistance network model is applicable to this, and will not be described herein. After the transistor resistance network model is established, all input combinations of standard units of each stage of all the time sequence paths to be processed can be exhausted by combining with a static time sequence analysis (STA) tool, and finally, equivalent resistance values are calculated according to the transistor resistance network model. The static time sequence analysis method can also be set with different accuracy such as PBA (Path Based Analysis), GBA (Graph Based Analysis), and the like, and will not be described herein.
Step S33, determining an equivalent resistance value AF i n corresponding to each a i n based on the mapping relationship corresponding to E m and F m, and determining a normalized logic level number B i n of a i n relative to the reference cell based on AF i n and G:
Bi n=AFi n/G。
The equivalent resistance value corresponding to each standard cell has been determined through steps S31 to S32, and therefore, in step S33, the equivalent resistance value AF i n corresponding to each a i n can be determined directly based on the mapping relationship corresponding to E m and F m. And then based on the proportional relation between the equivalent resistance value corresponding to A i n and the resistance value of the reference unit, the normalized logic level B i n of A i n relative to the reference unit can be accurately determined.
As an embodiment, if the timing risk timing path occurs in step S4, step S5 is performed:
And S5, returning the chip design code corresponding to the risk time sequence path to generate an updated chip design code.
And S6, carrying out logic synthesis based on the updated chip design code to generate an updated gate-level netlist, taking the updated gate-level netlist as the gate-level netlist to be processed, and returning to the step S2.
It should be noted that, the steps S2 to S6 may be performed repeatedly, and the sequential risk timing path does not occur in the step S4, so that the subsequent operations such as physical layout and routing, ECO, etc. may be continuously performed. It can be understood that if the time sequence risk time sequence path does not appear when the steps S1-S4 are executed for the first time, the subsequent operations such as physical layout and wiring, ECO and the like are directly continued to be executed. The method and the device perform accurate time sequence risk prediction in the gate-level netlist after updating based on logic synthesis, can find the time sequence risk problem of chip design at earlier stage, timely return chip design code modification, avoid subsequent execution of excessive useless operations, and improve chip development efficiency.
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The embodiment of the invention also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the methods of embodiments of the present invention.
The embodiment of the invention also provides a computer readable storage medium, which stores computer executable instructions for executing the method according to the embodiment of the invention.
According to the embodiment of the invention, the reference unit is selected, the logic level threshold is determined based on the reference unit, all the time sequence paths to be processed are normalized based on the reference unit, the total normalized logic level of the time sequence paths to be processed, and the time sequence risk time sequence paths are predicted based on the total normalized logic level of the time sequence paths to be processed and the logic level threshold. The method can realize accurate chip time sequence risk prediction based on the gate-level netlist generated by logic synthesis, and improves chip development efficiency.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (6)
1. The method for predicting the chip time sequence risk is characterized by comprising the following steps of:
S1, selecting a reference unit, and determining a normalized logic level threshold R based on the reference unit;
the step S1 includes:
Step S11, selecting a reference unit, and acquiring delay time t corresponding to transmission data of the reference unit;
step S12, obtaining a target frequency F and a target frequency allowance F;
step S13, determining a normalized logic level threshold R based on the delay time t, the target frequency F and the target frequency margin F:
R=（F-f）/t；
Step S2, obtaining all to-be-processed time sequence paths { A 1,A2,…,An,…,AN } in a to-be-processed gate-level netlist, wherein the to-be-processed gate-level netlist is generated by logic synthesis based on chip design codes, A n is an N-th to-be-processed time sequence path, N is a range of values from 1 to N, N is an i-th standard unit corresponding to A n in total number ,An={A1 n,A2 n,...,Ai n,...Af(n) n},Ai n of to-be-processed time sequence paths in the gate-level netlist, i is a range of values from 1 to f (N), and f (N) is a standard unit series corresponding to A n;
Step S3, obtaining a normalized logic level number B i n of each a i n relative to the reference unit, and obtaining a total normalized logic level number C i n corresponding to a n based on B i n:
Ci n=；
In the step S3, obtaining a normalized logic level number B i n of each a i n with respect to the reference cell includes:
Step S31, obtaining a standard cell library { D 1,D2,...,Dm,...,DM},Dm corresponding to the chip design is an mth standard cell in the standard cell library corresponding to the chip design, wherein the value range of M is 1 to M, and M is the total number of standard cells in the standard cell library corresponding to the chip design;
step S32, a transistor resistance network model E m corresponding to each standard cell D m is established according to the equivalent resistance from the source to the drain corresponding to each standard cell D m, a transistor resistance network model corresponding to the reference cell is established according to the equivalent resistance from the source to the drain corresponding to the reference cell, and an equivalent resistance F m corresponding to E m and an equivalent resistance G of the transistor resistance network model corresponding to the reference cell are obtained;
step S33, determining an equivalent resistance value AF i n corresponding to each a i n based on the mapping relationship corresponding to E m and F m, and determining a normalized logic level number B i n of a i n relative to the reference cell based on AF i n and G:
Bi n=AFi n/G；
Step S4, comparing each C i n with the logic level number threshold R, and determining A n with C i n larger than the logic level number threshold R as the time sequence risk time sequence path.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
And selecting a standard cell with highest appearance frequency in the chip design as a reference cell.
3. The method of claim 1, wherein the step of determining the position of the substrate comprises,
In the step S11, the component with the highest occurrence frequency in the chip design is selected as the reference unit.
4. The method of claim 1, wherein the step of determining the position of the substrate comprises,
If the timing risk timing path occurs in step S4, step S5 is executed:
S5, returning a chip design code corresponding to the risk time sequence path to be modified, and generating an updated chip design code;
And S6, carrying out logic synthesis based on the updated chip design code to generate an updated gate-level netlist, taking the updated gate-level netlist as the gate-level netlist to be processed, and returning to the step S2.
5. An electronic device, comprising:
At least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-4.
6. A computer readable storage medium, characterized in that computer executable instructions are stored for performing the method of any of the preceding claims 1-4.
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